3 Typical Application

The first example is a typical application which input voltage is 12 V, output voltage is 1.5 V. In the following examples, input voltage and output voltage do not change. It only changes inductance or output capacitance to see how they affect loop stability. And output capacitance uses GRM21BR61A226ME44 which is introduced in previous chapter.

Based on Equation 4, if LIR is set to 0.4, calculated inductance is 1.89uH. This example inductor uses 1.5uH.

Based on Equation 6, output capacitance should be 42.3uF. The output capacitance degrades by 10% at 1.5 V bias voltage. The effective capacitance is 19.8uF. Here output capacitance uses 2pcs capacitance. The total effective capacitance is 39.6uF. Double pole should be 20.6kHz. The schematic is shown in Figure 3-1.

Figure 3-1 Schematic of 12Vin to 1.5Vout

By using frequency response analyzer to run AC analysis, bode plot is shown in Figure 3-2. Double pole is about 20kHz. Internal zero is 24kHz. After double pole gain curve decreases at -40dB per decade rate. And after zero point it decreases at -20dB/Dec. The ESR of MLCC capacitance is very small about 2mohm, so zero frequency is very high about 1.88MHz which doesn’t have any effect on bandwidth and phase. Crossover frequency is 152.64kHz. Phase margin is 46 degree. It’s stable and bandwidth is large, so it has good load transient response.

Figure 3-2 Bode Plot of 12Vin to 1.5Vout with 1.5uH Inductor and 2x22uF Capacitance

Some might be curious about the result that double pole is set to be higher or lower than 20kHz or what is the range of double pole. The following uses several cases to explain the process.

If setting double pole to 10kHz, it needs to increase inductor and output capacitance together. Based on Equation 4, if LIR is set to 0.2, calculated inductance is 3.77uH. In this case inductor uses 3.3uH. Based on Equation 6, calculated capacitance is 76.8uF. Here output capacitance uses 4pcs 22uF capacitance.

Use frequency response analyzer to run AC analysis. Bode plot shown in Figure 3-3. Double pole is about 10kHz which match with calculated value. At 10kHz, gain curve begin to decrease at -40dB/Dec. After 24kHz, slew rate changes to -20dB/Dec. So bandwidth is smaller which is 55kHz. At 10kHz, phase drops too much because of double pole effect. Then phase curve begins to increase slowly by the effect of internal zero. Phase margin is 44 degree.

Figure 3-3 Bode Plot of 12Vin to 1.5Vout with 3.3uH Inductor and 4x22uF Capacitance

In this condition, it is suggested to add a 100pF CFF to increase phase margin. This CFF capacitance will increase a zero point and a pole point which frequency are as shown in Equation 7.

Equation 7.

Based on Equation 7, f_{CFF_zero} is 185kHz, f_{CFF_pole} is 346kHz. So this CFF zero point only increases phase from 18.5kHz, and doesn’t have an effect on gain. Figure 3-4 is tested bode plot with 100pF CFF. Bandwidth is still 59kHz and phase margin improves to 55 degree.

Figure 3-4 Bode Plot of 12Vin to 1.5Vout with 3.3uH Inductor, 4x22uF Capacitance and 100pF CFF

Another condition about lower double pole is to add a bulk output capacitance. Sometimes customers like to add a bulk capacitance at output port such as 100uF or even 220uF. Normally this kind of bulk capacitance has larger ESR. Larger ESR and bulk output capacitance make the frequency of zero small. So in this conditions ESR zero point couldn’t be ignored. Because it affects bandwidth and phase.

Based on previous case of 1.5uH inductor and 2x22uF output capacitance, it adds another 220uF electronic capacitance which ESR is 25m ohm. The double pole frequency is 8kHz. And ESR zero frequency is 24.3kHz. Figure 3-5 is tested bode plot. After double pole, there is an ESR zero at 24.3kHz and internal zero at 24kHz. So gain curve becomes flat after 30kHz. The gain curve will drop at a pole frequency which is added by internal Ramp circuit. The pole frequency of TPS563202 is about 200kHz. Because ESR zero is in bandwidth, it makes bandwidth large.

Figure 3-5 Bode Plot of 12Vin to 1.5Vout with 1.5uH Inductor and 2x22uF+220uF Capacitance

If setting double pole to 30kHz, inductor still uses 1.5uH, and calculated capacitance is 18.8uF based on Equation 6. It uses only one 22uF capacitance. Figure 3-6 is tested bode plot. Double pole is 30kHz, bandwidth is 262kHz. In high frequency the on time delay(Hds) makes phase drop quickly. Phase is only 24 degree. So it’s not suggested to put double pole after internal zero.

Figure 3-6 Bode Plot of 12Vin to 1.5Vout with 1.5uH Inductor and 22uF Capacitance

From the examples, it is suggested to set double pole marginally before internal zero. It can get large bandwidth and good phase margin. Also, it is not a problem to set double pole before or largely before internal zero. And in this condition, it is suggested to add a CFF capacitance to increase phase margin. Finally it’s not suggested to put double pole after internal zero.