DC/DC converters using D-CAP, D-CAP2, and D-CAP3 control architectures, referred to as D-CAPx in this report, became popular for their fast transient response with minimal output capacitance and their simplicity by eliminating external compensation components. The D-CAPx control architecture, a derivative of non-linear constant on-time control, poses a challenge for designers when measuring the control-loop gain. As Figure 1-1 shows, breaking the control loop is the proper technique for traditional linear control architectures, like voltage-mode control and current-mode control, where there is only one output feedback path. But when measuring the control-loop gain for D-CAPx architectures, a different approach is necessary. The D-CAPx control architecture has two direct output feedback paths as shown in Figure 1-2: one through the feedback resistor divider network R_up and R_low, and the other through the direct current resistance (DCR) injection circuit R_p, C_p, and C_ff. The D-CAPx control system does not have a high DC gain error amplifier like the traditional type II or type III compensator of current-mode or voltage-mode control architectures, where the FB pin is usually the negative input of the error amplifier. For D-CAPx converters, the FB pin is only one of the inputs of the PWM comparator. By leaving out one of the feedback path outputs of the measurement, the Bode plot measured using the setup in Figure 1-1 does not directly correlate to the transient response waveforms. To properly measure the loop-gain Bode plot, the loop breaking point must include both feedback paths, as Figure 1-3 shows.

For D-CAPx regulators, the PWM modulation gain is determined by the falling slope of the triangular waveform formed at the FB pin by the DCR injection network and output-capacitor equivalent series resistance (ESR). The parasitic inductance and resistance along the injection cable and noise coupled into the wires distorts the triangular waveform at the FB pin, which renders a different PWM modulation gain than the regulator with an improper test setup. To preserve accuracy, a bypass capacitor, C_pass, is added in parallel to a 20-Ω resistor by forming a high-pass filter. The corner frequency is set lower than one-half of the switching frequency of the converter so that the triangular waveform at the FB pin during the testing remains similar to that during normal operation. A 0.22 µF capacitor is used for a converter switching at 500 Hz in this example. For most applications, the proper C_pass value would be from 0.1 µF to 0.47 µF. To minimize the effect on the system, the DCR injection capacitor, C_p, should be less than one-tenth of C_pass, as Figure 1-3 shows.