SLUAAV9 March   2024 LM76003 , UCC27201A , UCC27282 , UCC27288

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design and Potential Risk in Certain Application Scenario
  6. 3Analysis of Potential Problem
    1. 3.1 High Duty Cycle Causes High Current Stress in Bootstrap Diode
      1. 3.1.1 Mode 1
      2. 3.1.2 Mode 2
      3. 3.1.3 Mode 3
      4. 3.1.4 Mode 4
    2. 3.2 Influence by the Extra Voltage Source
  7. 4Design Recommendation
  8. 5Summary
  9. 6References

Introduction

Solar optimizer is frequently used in string inverter system to maximize the output power of the solar panel. To achieve this goal, MPPT (Maximum Power Point Tracking) algorithm is widely used in the control of optimizer. MPPT's basic logic is to adjust the output voltage of optimizer which means adjust duty cycle of FETs to match output impendence. Buck topology is often used in optimizer. Once the output voltage of solar panel is equal or lower than the output voltage of buck converter when it operates in maximum power point, optimizer can go into pass through mode.

In pass through mode, the output power of solar panel can directly pass to the output of optimizer, and it is required high side FET of buck converter to operate with 100% duty cycle and low side FET to turn off.

In practice, the PWM signal of FETS can work in complementary with dead time. And the duty cycle of both FET can not go straight into 100% for high side FET or from 50% to 0% for the low side FET. Assume both duty cycle of FETs is 50% to achieve MPPT. And if from this moment light intensity consistently drops down, so the input voltage of optimizer which is also the output voltage of solar panel can decrease correspondingly. Once the controller detects that output voltage is below the threshold, duty cycle of high side FET can gradually increase to 100%.

There are two steps to consider if we want half-bridge gate driver to be used successfully in previously mentioned scenario. The first step is how to achieve 100% duty cycle for high side FET and the other step is what risk we can meet during the design and how to solve it.