SLUP412 February   2022 LMG3522R030-Q1

 

  1. 1 Introduction
  2. 2 Comparing Different Technologies
  3. 3 Advantages of Integrating the Driver With GaN FETs
  4. 4 The GaN-Based 6.6-kW OBC Reference Design
  5. 5 PFC Stage
  6. 6 DC/DC Stage
  7. 7 DC/DC Topology Selection
  8. 8 Frequency Selection
  9. 9 Core Loss
  10. 10Loss of ZVS
  11. 11Dead Time
  12. 12ISR Bandwidth
  13. 13Overall
  14. 14Resonant Tank Design
  15. 15Thermal Solution
  16. 16Layout Best Practices
  17. 17Control-Loop Considerations
  18. 18Conclusions
  19. 19References
  20. 20Important Notice

11 Dead Time

The time required for ZVS is a function of the parasitic capacitance connected to the switch node and the current source driving that capacitance, which tends to be dominated by the GaN FET short-circuit output capacitance (COSS). In order to avoid hard switching, the CLLLC converter needs to allow this voltage to transition in a resonant manner. Since facilitating these transitions consumes a significant portion of the tank energy, the dead time essentially reduces the efficiency since no meaningful power transfer occurs. As the switching frequency becomes large, the overall dead time can become a significant percentage of the overall switching period.