The TPS54383 and TPS54386 are dual output, non-synchronous buck converters capable of supporting 3-A output applications that operate from a 4.5-V to 28-V input supply voltage, and require output voltages between 0.8 V and 90% of the input voltage.
With an internally-determined operating frequency, soft-start time, and control loop compensation, these converters provide many features with a minimum of external components. Channel 1 overcurrent protection is set at 4.5 A, while Channel 2 overcurrent protection level is selected by connecting a pin to ground, to BP, or left floating. The setting levels are used to allow for scaling of external components for applications that do not need the full load capability of both outputs.
The outputs may be enabled independently, or may be configured to allow either ratio-metric or sequential startup sequencing. Additionally, the two outputs may be powered from different sources.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54383 | HTSSOP (14) | 4.40 mm × 5.00 mm |
TPS54386 |
Changes from B Revision (October 2007) to C Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BOOT1 | 2 | I | Input supply to the high side gate driver for Output 1. Connect a 22-nF to 82-nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor. |
BOOT2 | 13 | I | Input supply to the high side gate driver for Output 2. Connect a 22-nF to 82-nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor. |
BP | 11 | - | Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7-μF to 10-μF X7R or X5R) ceramic capacitor. |
EN1 | 5 | I | Active low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 1 and allows soft-start of Output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation. |
EN2 | 6 | I | Active low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft-start of Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation. |
FB1 | 7 | I | Voltage feedback pin for Output 1. The internal transconductance error amplifier adjusts the PWM for Output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Output 1 to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information. |
FB2 | 8 | I | Voltage feedback pin for Output 2. The internal transconductance error amplifier adjusts the PWM for Output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Output 2 to ground, with the center connection tied to this pin, determines the value of the regulated Output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information. |
GND | 4 | - | Ground pin for the device. Connect directly to Thermal Pad. |
ILIM2 | 9 | I | Current limit adjust pin for Output 2 only. This function is intended to allow a user with asymmetrical load currents (Output 1 load current much greater than Output 2 load current) to optimize component scaling of the lower current output while maintaining proper component derating in a overcurrent fault condition. The discrete levels are available as shown in Table 2. Note: An internal 2-resistor divider (150-kΩ each) connects BP to ILIM2 and to GND. |
PVDD1 | 1 | I | Power input to the Output 1 high side MOSFET only. This pin should be locally bypassed to GND with a low ESR ceramic capacitor of 10-μF or greater. |
PVDD2 | 14 | I | The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins and provides power to the Output 2 high-side MOSFET. This pin should be locally bypassed to GND with a low ESR ceramic capacitor of 10-μF or greater. The UVLO function monitors PVDD2 and enables the device when PVDD2 is greater than 4.1 V. |
SEQ | 10 | I | This pin configures the output startup mode. If the SEQ pin is connected to BP, then when Output 2 is enabled, Output 1 is allowed to start after Output 2 has reached regulation; that is, sequential startup where Output 1 is slave to Output 2. If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN1 to ground. If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start after Output 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN2 to ground. If left floating, Output 1 and Output 2 start ratio-metrically when both outputs are enabled at the same time. They will soft-start at a rate determined by their final output voltage and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate independently NOTE: An internal two resistor (150-kΩ each) divider connects BP to SEQ and to GND. See the Sequence States table. |
SW1 | 3 | O | Source (switching) output for Output 1 PWM. A snubber is recommended to reduce ringing on this node. See SW Node Ringing for further information. |
SW2 | 12 | O | Source (switching) output for Output 2 PWM. A snubber is recommended to reduce ringing on this node. See SW Node Ringing for further information. |
Thermal Pad | — | — | This pad must be tied externally to a ground plane and the GND pin. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage range | PVDD1, PVDD2, EN1, EN2 | 30 | V | |
BOOT1, BOOT2 | VSW+ 7 | |||
SW1, SW2 | –2 | 30 | ||
SW1, SW2 transient (< 50ns) | –3 | 31 | ||
BP | 6.5 | |||
SEQ, ILIM2 | –0.3 | 6.5 | ||
FB1, FB2 | –0.3 | 3 | ||
SW1, SW2 output current | 7 | A | ||
BP load current | 35 | mA | ||
TJ | Operating temperature | –40 | +150 | °C |
Soldering temperature | +260 | |||
Tstg | Storage temperature | –55 | 165 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VPVDD2 | Input voltage | 4.5 | 28 | V | |
TJ | Operating junction temperature | –40 | +125 | °C |
THERMAL METRIC(1) | TPS54383 TPS54386 | UNIT | |
---|---|---|---|
HTSSOP | |||
14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 48.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 29.4 | |
RθJB | Junction-to-board thermal resistance | 25.1 | |
ψJT | Junction-to-top characterization parameter | 0.9 | |
ψJB | Junction-to-board characterization parameter | 24.9 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.4 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT SUPPLY (PVDD) | |||||||
VPVDD1 | Input voltage range | 4.5 | 28 | V | |||
VPVDD2 | |||||||
IDDSDN | Shutdown | VEN1 = VEN2 = VPVDD2 | 70 | 150 | μA | ||
IDDQ | Quiescent, non-switching | VFB = 0.9 V, Outputs off | 1.8 | 3.0 | mA | ||
IDDSW | Quiescent, while-switching | SW node unloaded; Measured as BP sink current | 5 | ||||
VUVLO | Minimum turn-on voltage | PVDD2 only | 3.8 | 4.1 | 4.4 | V | |
VUVLO(hys) | Hysteresis | 400 | mV | ||||
tSTART(1)(2) | Time from startup to softstart begin | CBP = 10 μF, EN1 and EN2 go low simultaneously | 2 | ms | |||
ENABLE (EN) | |||||||
VEN1 | Enable threshold | 0.9 | 1.2 | 1.5 | V | ||
VEN2 | |||||||
Hysteresis | 50 | mV | |||||
IEN1 | Enable pull-up current | VEN1 = VEN2 = 0 V | 6 | 12 | μA | ||
IEN2 | |||||||
tEN(1) | Time from enable to soft-start begin | Other EN pin = GND | 10 | μs | |||
BP REGULATOR (BP) | |||||||
BP | Regulator voltage | 8 V < PVDD2 < 28 V | 5 | 5.25 | 5.6 | V | |
BPLDO | Dropout voltage | PVDD2 = 4.5 V; switching, no external load on BP | 400 | mV | |||
IBP(1) | Regulator external load | 2 | mA | ||||
IBPS | Regulator short circuit | 4.5 V < PVDD2 < 28 V | 10 | 20 | 30 | ||
OSCILLATOR | |||||||
fSW | Switching frequency | TPS54383 | 255 | 310 | 375 | kHz | |
TPS54386 | 510 | 630 | 750 | ||||
tDEAD(1) | Clock dead time | 140 | ns | ||||
ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF) | |||||||
VFB1 | Feedback input voltage | 0°C < TJ < +85°C | 788 | 800 | 812 | mV | |
VFB2 | –40°C < TJ < +125°C | 786 | 812 | ||||
IFB1 | Feedback input bias current | 3 | 50 | nA | |||
IFB2 | |||||||
gM1(1) | Transconductance | 30 | μS | ||||
gM2(1) | |||||||
SOFT-START (SS) | |||||||
TSS1 | Soft-start time | 1.5 | 2.1 | 2.7 | ms | ||
TSS2 | |||||||
OVERCURRENT PROTECTION | |||||||
ICL1 | Current limit channel 1 | 3.6 | 4.5 | 5.6 | A | ||
ICL2 | Current limit channel 2 | VILIM2 = VBP | 3.6 | 4.5 | 5.6 | ||
VILIM2 = (floating) | 2.4 | 3.0 | 3.6 | ||||
VILIM2 = GND | 1.15 | 1.50 | 1.75 | ||||
VUV1 | Low-level output threshold to declare a fault | Measured at feedback pin. | 670 | mV | |||
VUV2 | |||||||
THICCUP(1) | Hiccup timeout | 10 | ms | ||||
tON1(oc)(1) | Minimum overcurrent pulse width | 90 | 150 | ns | |||
tON2(oc)(1) | |||||||
BOOTSTRAP | |||||||
RBOOT1 | Bootstrap switch resistance | From BP to BOOT1 or BP to BOOT2, IEXT = 50 mA |
18 | Ω | |||
RBOOT2 | |||||||
OUTPUT STAGE (Channel 1 and Channel 2) | |||||||
RDS(on)(1) | MOSFET on resistance plus bond wire resistance | TJ = +25°C, VPVDD2 = 8 V | 85 | mΩ | |||
–40°C < TJ < +125°C, VPVDD2 = 8 V | 85 | 165 | |||||
tON(min)(1) | Minimum controllable pulse width | ISWx peak current > 1 A(3) | 100 | 200 | ns | ||
DMIN | Minimum Duty Cycle | VFB = 0.9 V | 0 | % | |||
DMAX | Maximum Duty Cycle | TPS54383 | fSW = 300 kHz | 90 | 95 | % | |
TPS54386 | fSW = 600 kHz | 85 | 90 | % | |||
ISW | Switching node leakage current (sourcing) | Outputs OFF | 2 | 12 | μA | ||
THERMAL SHUTDOWN | |||||||
TSD(1) | Shutdown temperature | 148 | °C | ||||
TSD(hys)(1) | Hysteresis | 20 |
The TPS54383 and TPS54386 are dual output, non-synchronous step down (buck) converters. Integrated into each PWM channel is an internally-compensated error amplifier, current mode pulse width modulator (PWM), switch MOSFET, internal bootstrap switch for high-side gate drive, and fault protection circuitry. Each channel also contains an EN pin and internal fixed soft-start time. The fault protection circuitry includes cycle-by-cycle current limit, output undervoltage detection, hiccup timeout and thermal shutdown. Channel 1 has a fixed current limit and channel 2 has three selectable overcurrent levels. Common to the two channels is the internal BP voltage regulator, voltage reference, clock oscillator, and output voltage sequencing functions.
DESIGN HINT
The TPS5438x contains internal slope compensation and loop compensation components; therefore, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. This approach differs from an externally-compensated controller, where the L-C filter is generally selected first, and the compensation network is found afterwards. (See Feedback Loop and L-C Filter Selection section.)
NOTE
Unless otherwise noted, the term TPS5438x applies to both the TPS54383 and TPS54386. Also, unless otherwise noted, a label with a lowercase x appended implies the term applies to both outputs of the two modulator channels. For example, the term ENx implies both EN1 and EN2. Unless otherwise noted, all parametric values given are typical. Refer to the Electrical Characteristics for minimum and maximum values. Calculations should be performed with tolerance values taken into consideration.
The bandgap cell common to both outputs, trimmed to 800 mV.
The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs are internally configured to operate on alternating switch cycles (that is, 180° out of phase).
When the voltage at the PVDD2 pin is less than 4.1 V, a portion of the internal bias circuitry is operational, and all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises above the UVLO turn-on threshold, the state of the enable pins determines the remainder of the internal startup sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with a 20-mA current. When the BP pin is greater than 4 V, PWM is enabled and soft-start begins, depending on the SEQ mode of operation and the EN1 and EN2 settings.
Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be higher or lower than PVDD2. (See the Dual Supply Operation section.)
Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, the associated output is enabled and soft-start is initiated.
If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator is shut down and minimal functions are active. The total standby current from both PVDD pins is approximately 70 μA at 12-V input supply.
An R-C connected to an ENx pin may be used to delay the turn-on of the associated output after power is applied to PVDDx (see Figure 16). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards ground. Once the voltage decays to approximately 1.2 V, then the output is enabled and the startup sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to PVDD2, then omit these two components and tie the ENx pin to GND directly.
If an R-C circuit is used to delay the turn-on of the output, the resistor value must be much less than 1.2 V / 6μA or 200 kΩ. A suggested value is 51 kΩ. This resistor value allows the ENx voltage to decay below the 1.2-V threshold while the 6-μA bias current flows.
The capacitor value required to delay the startup time (after the application of PVDD2) is shown in Equation 1.
where
Other enable pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencing section.)
DESIGN HINT
If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to GND. This configuration allows the outputs to start immediately on valid application of PVDD2.
If ENx is allowed to go high after the Outputx has been in regulation, the upper MOSFET shuts off, and the output decays at a rate determined by the output capacitor and the load. The internal pulldown MOSFET remains in the OFF state. (See the Bootstrap for N-Channel MOSFET section.)
The TPS5438x allows single-pin programming of output voltage startup sequencing. During power-on, the state of the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs behave as described in Table 1.
SEQ PIN STATE | MODE | EN1 | EN2 |
---|---|---|---|
BP | Sequential, Output 2 then Output 1 | Ignored by the device.when VEN2 < enable threshold voltage | Active |
Tie EN1 to < enable threshold voltage for BP to be active when VEN2 > enable threshold voltage | |||
Tie EN1 to > enable threshold voltage for low quiescent current (BP inactive) when VEN2 > enable threshold voltage | |||
GND | Sequential, Output 1 then Output 2 | Active | Ignored by the device.when VEN1 < enable threshold voltage |
Tie EN2 to < enable threshold voltage for BP to be active when VEN1 > enable threshold voltage | |||
Tie EN2 to > enable threshold voltage for low quiescent current (BP inactive) when VEN1 > enable threshold voltage | |||
(floating) | Independent or Ratiometric, Output 1 and Output 2 | Active. EN1 and EN2 must be tied together for Ratio-metric startup. | Active. EN1 and EN2 must be tied together for Ratio-metric startup. |
If the SEQ pin is connected to BP, then when Output 2 is enabled, Output 1 is allowed to start approximately 400 μs after Output 2 has reached regulation; that is, sequential startup where Output 1 is slave to Output 2. If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present.
If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start approximately 400 μs after Output 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present.
NOTE
An R-C network connected to the ENx pin may be used in addition to the SEQ pin in sequential mode to delay the startup of the first output voltage. This approach may be necessary in systems with a large number of output voltages and elaborate voltage sequencing requirements. SeeEnable and Timed Turn On of the Outputs.
If the SEQ pin is left floating, Output 1 and Output 2 each start ratiometrically when both outputs are enabled at the same time. Output 1 and Output 2 soft-start at a rate that is determined by the respective final output voltages and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate independently.
Each output has a dedicated soft-start circuit. The soft-start voltage is an internal digital reference ramp to one of two noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 2.1 ms. During a soft-start interval, the TPS5438x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the output voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches the internal 0.8 V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains at the reference voltage.
NOTE
To avoid a disturbance in the output voltage during the stepping of the digital soft -tart, a minimum output capacitance of 50μF is recommended. See Feedback Loop and Inductor-Capacitor (L-C) Filter Selection Once the filter and compensation components have been established, laboratory measurements of the physical design should be performed to confirm converter stability.
During the soft-start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six PWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See the Output Overload Protection section.) There is no pulse skipping if a current limit pulse is not detected.
DESIGN HINT
If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired regulation voltage by the time Soft-Start has completed, then the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed delay startup from the ENx pin to delay the startup of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage. See Operating Near Maximum Duty Cycleand Maximum Output Capacitance for related information.
Each output has a dedicated feedback loop comprised of a voltage setting divider, an error amplifier, a pulse width modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and GND (see Figure 21). Assuming the value of the upper voltage setting divider is known, the value of the lower divider resistor for a desired output voltage is calculated by Equation 2.
where
DESIGN HINT
There is a leakage current of up to 12 μA out of the SW pin when a single output of the TPS5438x is disabled. Keeping the series impedance of R1 + R2 less than 50 kΩ prevents the output from floating above the reference voltage while the controller output is in the OFF state.
In the feedback signal path, the output voltage setting divider is followed by an internal gM-type error amplifier with a typical transconductance of 30 μS. An internal series connected R-C circuit from the gM amplifier output to ground serves as the compensation network for the converter. The signal from the error amplifier output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal-fed to drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure 22.
NOTE
Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow pulse width operation, especially at load currents less than 1 A. See SW Node Ringing for further information on reducing noise on the SWx node.
A more conventional small signal equivalent block diagram is shown in Figure 23. Here, the full closed loop signal path is shown. Because the TPS5438x contains internal slope compensation and loop compensation components, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. This approach differs from an externally-compensated controller, where the L-C filter is generally selected first, and the compensation network is found afterwards. To find the appropriate L and C filter combination, the Output-to-Vc signal path plots (see the next section) of gain and phase are used along with other design criterial to aid in finding the combinations that best results in a stable feedback loop.
The following figures plot the TPS5438x Output-to-Vc gain and phase versus frequency for various duty cycles (10%, 30%, 50%, 70%, 90%) at three (200 mA, 400 mA, 600 mA) peak-to-peak ripple current levels. The loop response curve selected to compensate the loop is based on the duty cycle of the application and the ripple current in the inductor. Once the curve has been selected and the inductor value has been calculated, the output capacitor is found by calculating the L-C resonant frequency required to compensate the feedback loop. A brief example follows the curves.
Note that the internal error amplifier compensation is optimized for output capacitors with an ESR zero frequency between 20 kHz and 60 kHz. See the following sections for further details.
With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance which may be used before startup problems begin to occur. If the output capacitance is large enough so that the device enters a current limit protection mode during startup, then there is a possibility that the output will never reach regulation. Instead, the TPS5438x simply shuts down and attempts a restart as if the output were short-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the load) is given by Equation 3:
Ensure the value of capacitance selected for closed loop stability is compatible with the requirements of Soft-Start.
Within the limits of the internal compensation, there is flexibility in the selection of the inductor and output capacitor values. A smaller inductor increases ripple current, and raises the resonant frequency, thereby incerasing the required amount of output capacitance. A smaller capacitor could also be used, increasing the resonant frequency, and increasing the overall loop bandwidth—perhaps at the expense of adequate phase margin.
The internal compensation of the TPS54x8x is designed for capacitors with an ESR zero frequency between 20kHz and 60kHz. It is possible, with additional feedback compensation components, to use capacitors with higher or lower ESR zero frequencies. For either case, the components C1 and R3 (ref.Figure 30 ) are added to re-compensate the feedback loop for stability. In this configuration a low frequency pole is followed by a higher frequency zero. The placement of this pole-zero pair is dependent on the type of output capacitor used, and the desired closed loop frequency response.
NOTE
Once the filter and compensation components have been established, laboratory measurements of the physical design should be performed to confirm converter stability.
If a high-ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to instability. To compensate, a small R-C series connected network is placed in parallel with the lower voltage setting divider resistor (see Figure 30). The values of the components are determined such that a pole is placed at the same frequency as the ESR zero and a new zero is placed at a frequency location conducive to good loop stability.
The value of the resistor is calculated using a ratio of impedances to match the ratio of ESR zero frequency to the desired zero frequency.
where
The value of the capacitor is calculated in Equation 5.
where
With low ESR ceramic capacitors, there may not be enough phase margin at the crossover frequency. In this case, (see Figure 30) resistor R3 is set equal to 1/2 R2. This lowers the gain by 6 dB, reduce the crossover frequency, and improve phase margin.
The value of C1 is found by determining the frequency to place the low frequency pole. The minimum frequency to place the pole is 1 kHz. Any lower, and the time constant will be too slow and interfere with the internal soft-start (see Soft-Start). The upper bound for the pole frequency is determined by the operating frequency of the converter. It is 3 kHz for the TPS54x83, and 6 kHz for the TPS54x86. C1 is then found from Equation 7. Keep component tolerances in mind when selecting the desired pole frequency.
where
If it is necessary to increase phase margin, place a capacitor in parallel with the upper voltage setting divider resistor (Ref. C2 in Equation 9).
where
First, the steady state duty cycle is calculated. Assuming the rectifier diode has a voltage drop of 0.5 V, the duty cycle is approximated using Equation 10.
The filter inductor is then calculated; see Equation 11.
A custom-designed inductor may be used for the application, or a standard value close to the calculated value may be used. For this example, a standard 10-μH inductor is used. Using Figure 28, find the 30% duty cycle curve. The 30% duty cycle curve has a down slope from low frequency and rises at approximately 6 kHz. This curve is the resonant frequency that must be compensated. Any frequency wthin an octave of the peak may be used in calculating the capacitor value. In this example, 6 kHz is used.
A 68-μF capacitor should be used as a bulk capacitor, with up to 10 μF of ceramic bypass capacitance. To ensure the ESR zero does not significantly impact the loop response, the ESR of the bulk capacitor should be placed a decade above the resonant frequency.
The resulting loop gain and phase are shown in Figure 31. Based on measurement, loop crossover is 45 kHz with a phase margin of 60 degrees.
A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%, allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive the MOSFET gate is derived from the voltage on this capacitor.
To allow the bootstrap capacitor to charge each switching cycle, an internal pulldown MOSFET (from SW to GND) is turned ON for approximately 140 ns at the beginning of each switching cycle. In this way, if, during light load operation, there is insufficient energy for the SW node to drive to ground naturally, this MOSFET forces the SW node toward ground and allow the bootstrap capacitor to charge.
Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge requirement of the MOSFET being used.
DESIGN HINT
For the bootstrap capacitor, use a ceramic capacitor with a value between 22 nF and 82 nF.
NOTE
For 5-V input applications, connect PVDDx to BP directly. This connection bypasses the internal control circuit regulator and provides maximum voltage to the gate drive circuitry. In this configuration, shutdown mode IDDSDN will be the same as quiescent IDDQ.
There is no special circuitry for pulse skipping at light loads. The normal characteristic of a nonsynchronous converter is to operate in the discontinuous conduction mode (DCM) at an average load current less than one-half of the inductor peak-to-peak ripple current. Note that the amplitude of the ripple current is a function of input voltage, output voltage, inductor value, and operating frequency, as shown in Equation 14.
Further, during discontinuous mode operation the commanded pulse width may become narrower than the capability of the converter to resolve. To maintain the output voltage within regulation, skipping switching pulses at light load conditions is a natural by-product of that mode. This condition may occur if the output capacitor is charged to a value greater than the output regulation voltage, and there is insufficient load to discharge the capacitor. A by-product of pulse skipping is an increase in the peak-to-peak output ripple voltage.
DESIGN HINT
If additional output capacitance is required to reduce the output voltage ripple during DCM operation, be sure to recheck Feedback Loop and Inductor-Capacitor (L-C) Filter Selection and Maximum Output Capacitance sections.
A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary to decrease the voltage waveform ringing at the SW node to less than 5 volts peak and of a duration of less than 30-ns. In addition to following good printed circuit board (PCB) layout practices, there are a couple of design techniques for reducing ringing and noise.
Voltage ringing observable at the SW node is caused by fast switching edges and parasitic inductance and capacitance. If the ringing results in excessive voltage on the SW node, or erratic operation of the converter, an R-C snubber may be used to dampen the ringing and ensure proper operation over the full load range.
DESIGN HINT
A series-connected R-C snubber (C = between 330 pF and 1 nF, R = 10 Ω) connected from SW to GND reduces the ringing on the SW node.
A small resistor in series with the bootstrap capacitor reduces the turn-on time of the internal MOSFET, thereby reducing the rising edge ringing of the SW node.
DESIGN HINT
A resistor with a value between 1Ω and 3Ω may be placed in series with the bootstrap capacitor to reduce ringing on the SW node.
DESIGN HINT
Placeholders for these components should be placed on the initial prototype PCBs in case they are needed.
In the event of an overcurrent during soft-start on either output (such as starting into an output short), pulse-by-pulse current limiting and PWM frequency division are in effect for that output until the internal soft-start timer ends. At the end of the soft-start time, a UV condition is declared and a fault is declared. During this fault condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON. This process ensures that both outputs discharge to GND in the event that overcurrent is on one output while the other is not loaded. The converter then enters a hiccup mode timeout before attempting to restart. "Frequency Division" means if an overcurrent pulse is detected, six clock cycles are skipped before a next PWM pulse is initiated, effectively dividing the operating frequency by six and preventing excessive current build up in the inductor.
In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is in effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (that follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON. This design ensures that both outputs discharge to GND, in the event that overcurrent is on one output while the other is not loaded. The converter then enters a hiccup mode timeout before attempting to restart.
The overcurrent threshold for Output 1 is set nominally at 4.5 A. The overcurrent level of Output 2 is determined by the state of the ILIM2 pin. The ILIM setting of Output 2 is not latched in place and may be changed during operation of the converter.
ILIM2 Connection | OCP Threshold for Output 2 |
---|---|
BP | 4.5 A nominal setting |
(floating) | 3.0 A nominal setting |
GND | 1.5 A nominal setting |
DESIGN HINT
The OCP threshold refers to the peak current in the internal switch. Be sure to add one-half of the peak inductor ripple current to the dc load current in determining how close the actual operating point is to the OCP threshold
If the TPS5438x operates at maximum duty cycle, and if the input voltage is insufficient to support the output voltage (at full load or during a load current transient), then there is a possibility that the output voltage will fall from regulation and trip the output UV comparator. If this should occur, the TPS5438x protection circuitry will declare a fault and enter a shut down-and-restart cycle.
DESIGN HINT
Ensure that under ALL conditions of line and load regulation, there is sufficient duty cycle to maintain output voltage regulation.
To calculate the operating duty cycle, use Equation 15.
where
It is possible to operate a TPS5438x from two supply voltages. If this application is desired, then the sequencing of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This level requirement ensures that the internal regulator and the control circuitry are in operation before PVDD1 supplies energy to the output. In addition, Output 1 must be held in the disabled state (EN1 high) until there is sufficient voltage on PVDD1 to support Output 1 in regulation. (See the Operating Near Maximum Duty Cycle section.)
The preferred sequence of events is:
With these two conditions satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1.
DESIGN HINT
An R-C delay on EN1 may be used to delay the startup of Output1 for a long enough period of time to ensure that PVDD1 can support Output 1 load.
It is possible to source PVDD1 from Output 2 as depicted in Figure 34 and Figure 35. This configuration may be preferred if the input voltage is high, relative to the voltage on Output 1.
In this configuration, the following conditions must be maintained:
The TPS5438x is not designed to operate as a two-channel multiphase converter. See http://www.power.ti.com for appropriate device selection.
As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noise immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible.
The overtemperature thermal protection limits the maximum power to be dissipated at a given operating ambient temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is limited by the maximum allowable junction operating temperature. The device junction temperature is a function of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature should reach the thermal shutdown level, the TPS5438x shuts off both PWMs and remains in this state until the die temperature drops below the hysteresis value, at which time the device restarts.
The first step to determine the device junction temperature is to calculate the power dissipation. The power dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by each MOSFET is composed of conduction losses and output (switching) losses incurred while driving the external rectifier diode. To find the conduction loss, first find the RMS current through the upper switch MOSFET.
where
Notice the impact of the operating duty cycle on the result.
Multiplying the result by the RDS(on) of the MOSFET gives the conduction loss.
The switching loss is approximated by:
where
The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal regulator.
The temperature rise of the device junction depends on the thermal impedance from junction to the mounting pad (See the Thermal Information table for performance on the standard test board), plus the thermal impedance from the thermal pad to ambient. The thermal impedance from the thermal pad to ambient depends on the PCB layout (PowerPAD interface to the PCB, the exposed pad area) and airflow (if any). See the Layout Guidelines section.
The operating junction temperature is shown in Equation 20.
The TPS5438x delivers full current at ambient temperatures up to +85°C if the thermal impedance from the thermal pad maintains the junction temperature below the thermal shutdown level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction temperature at or below the thermal shutdown level. Figure 36 illustrates the power derating for elevated ambient temperature under various airflow conditions. Note that these curves assume that the PowerPAD is properly soldered to the recommended thermal pad. (See the Related Documentation section for further information.)
The TPS5438x is recommended to operate with input voltages above 4.5 V. The typical UVLO threshold is 4.1 V at PVDD2 and the device may operate at PVDD2 voltages down to the UVLO voltage. PVDD2 is used for input voltage UVLO protection because it is the power supply for the BP regulator. The device will operate with PVDD1 voltages even lower as long as PVDD2 is above its UVLO threshold. With VPVDD2 below the UVLO voltage threshold the device will not switch. If either ENx pins is pulled below 0.9 V, when VPVDD2 passes the UVLO threshold the BP regulator turns on and begins charging the BP capacitor. After VBP is greater than 4 V, depending on the state of the SEQ pin, the channel corresponding to the low ENx pin will become active. When a channel becomes active switching is enabled and the soft-start sequence is initiated. The TPS5438x starts linearly ramping up an internal soft-start reference voltage of the active channel from 0 V to its final value over the internal soft-start time period. The designer should make sure the input voltage is sufficient to support the output voltage of the active channels.
The enable start threshold voltage is 1.2 V typical. With ENx held above the 1.2 V threshold voltage the correspondeng cahnnel of the TPS548x is disabled and switching is inhibited even if PVDD2 is above its UVLO threshold. The quiescent current is reduced in this state. When the first ENx pin voltage is decreased below the threshold while V(PVDD2) is above the UVLO threshold the BP regulator turns on and begins charging the BP capacitor. After VBP is greater than 4 V, depending on the state of the SEQ pin, the channel corresponding to the low ENx pin will become active. If the second ENx pin voltage is decreased below the threshold after VBP is greater than 4 V, again depending on the state of the SEQ pin, the corresponding channel will become active immediately. When a channel becomes active switching is enabled and the slow-start sequence is initiated. The TPS548x starts linearly ramping up the internal soft-start reference voltage of the active channel from 0 V to its final value over the internal slow-start time period. If both channels are active the start-up sequence is deteremined by the stat of the SEQ pin. The designer should make sure the input voltage is sufficient to support the output voltageof the active channels.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS5438x is a dual 28-V, 3-A, step down regulator with an integrated high-side MOSFETs. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 3 A on each channel. Example applications are: High Density Point-of-Load Regulators for Set-top Box, Digital TV, Power for DSP and other Consumer Electronics.
The following example illustrates a design process and component selection for a 12-V to 5-V and 3.3-V dual non-synchronous buck regulator using the TPS54383 converter.
PARAMETER | NOTES AND CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
VIN | Input voltage | 6.9 | 12.0 | 13.2 | V | |
IIN | Input current | VIN = nom, IOUT = max | 1.6 | 2.0 | A | |
No load input current | VIN = nom, IOUT = 0 A | 12 | 20 | mA | ||
OUTPUT CHARACTERISTICS | ||||||
VOUT1 | Output voltage 1 | VIN = nom, IOUT = nom | 4.8 | 5.0 | 5.2 | V |
VOUT2 | Output voltage 2 | VIN = nom, IOUT = nom | 3.2 | 3.3 | 3.4 | |
Line regulation | VIN = min to max | 1% | ||||
Load regulation | IOUT = min to max | 1% | ||||
VOUT(ripple) | Output voltage ripple | VIN = nom, IOUT = max | 50 | mVPP | ||
IOUT1 | Output current 1 | VIN = min to max | 0 | 2.0 | A | |
IOUT2 | Output current 2 | VIN = min to max | 0 | 2.0 | ||
IOCP1 | Output overcurrent channel 1 | VIN = nom, VOUT = VOUT1 = 5% | 2.4 | 3 | 3.5 | |
IOCP2 | Output overcurrent channel 2 | VIN = nom, VOUT = VOUT2 = 5% | 2.4 | 3 | 3.5 | |
Transient response ΔVOUT from load transient | ΔIOUT = 1 A @ 3 A/μs | 200 | mV | |||
Transient response settling time | 1 | ms | ||||
SYSTEM CHARACTERISTICS | ||||||
fSW | Switching frequency | 250 | 310 | 370 | kHz | |
η | Full load efficiency | 85% | ||||
TJ | Operating temperature range | 0 | 25 | 60 | °C |
QTY | REFERENCE DESIGNATOR |
VALUE | DESCRIPTION | SIZE | PART NUMBER | MANUFACTURER |
---|---|---|---|---|---|---|
1 | C1 | 100 μF | Capacitor, Aluminum, 25V, 20% | E-can | EEEFC1E101P | Panasonic |
2 | C10, C11 | 10 μF | Capacitor, Ceramic, 25V, X5R 20% | 1210 | C3216X5R1E106M | TDK |
1 | C12 | 4.7 μF | Capacitor, Ceramic, 10V, X5R 20% | 0805 | Std | Std |
2 | C14, C16 | 470 pF | Capacitor, Ceramic, 25V, X7R, 20% | 0603 | Std | Std |
1 | C15 | 6.8 nF | Capacitor, Ceramic, 25V, X7R, 20% | 0603 | Std | Std |
1 | C17, C5 | 100 μF | Capacitor, Aluminum, 10V, 20%, FC Series | F-can | EEEFC1A101P | Panasonic |
4 | C3, C4, C18, C19 | 10 μF | Capacitor, Ceramic, 6.3V, X5R 20% | 0805 | C2012X5R0J106M | TDK |
1 | C8 | 10 nF | Capacitor, Ceramic, 25V, X7R, 20% | 0603 | Std | Std |
2 | C9, C13 | 0.033 μF | Capacitor, Ceramic, 25V, X7R, 20% | 0603 | Std | Std |
2 | D1, D2 | MBRS320 | Diode, Schottky, 3-A, 30-V | SMC | MBRS330T3 | On Semi |
2 | L1, L2 | 22 μH | Inductor, Power, 6.8A, 0.038 Ω | 0.484 x 0.484 | MSS1278-153ML | Coilcraft |
2 | R2, R9 | 20 kΩ | Resistor, Chip, 1/16W, 1% | 0603 | Std | Std |
1 | R5 | 422 Ω | Resistor, Chip, 1/16W, 1% | 0603 | Std | Std |
2 | R6, R10 | 10 Ω | Resistor, Chip, 1/16W, 5% | 0603 | Std | Std |
1 | R8 | 698 Ω | Resistor, Chip, 1/16W, 1% | 0603 | Std | Std |
1 | R4 | 3.83 kΩ | Resistor, Chip, 1/16W, 1% | 0603 | Std | Std |
1 | R7 | 6.34 kΩ | Resistor, Chip, 1/16W, 1% | 0603 | Std | Std |
1 | U1 | TPS54383 DC-DC Switching Converter w/ FET | HTSSOP-14 | TPS54383PWP | TI |
Use the following design procedure to select component values for the TPS5438x.
The first step is to estimate the duty cycle of each switching FET.
Using an assumed forward drop of 0.5 V for a schottky rectifier diode, the Channel 1 duty cycle is approximately 40.1% (minimum) to 48.7% (maximum) while the Channel 2 duty cycle is approximately 27.7% (minimum) to 32.2% (maximum).
The peak-to-peak ripple is limited to 30% of the maximum output current. This places the peak current far enough from the minimum overcurrent trip level to ensure reliable operation.
For both Channel 1 and Channel 2, the maximum inductor ripple current is 600 mA. The inductor size is estimated in Equation 23.
The inductor values are
The next higher standard inductor value of 22 μH is used for both inductors.
The resulting ripple currents are :
Peak-to-peak ripple currents of 0.498 A and 0.416 A are estimated for Channel 1 and Channel 2 respectively.
The RMS current through an inductor is approximated by Equation 25.
and is approximately 2.0 A for both channels.
The peak inductor current is found using:
An inductor with a minimum RMS current rating of 2.0 A and minimum saturation current rating of 2.25 A is required. A Coilcraft MSS1278-223ML 22-μH, 6.8-A inductor is selected.
A schottky diode is selected as a rectifier diode for its low forward voltage drop. Allowing 20% over VIN for ringing on the switch node, the required minimum reverse break-down voltage of the rectifier diode is:
The diode must have reverse breakdown voltage greater than 15.8 V, therefore a 20-V device is used.
The average current in the rectifier diode is estimated by Equation 28.
For this design, 1.2-A (average) and 2.25 A (peak) is estimated for Channel 1 and 1.5-A (average) and 2.21-A (peak) for Channel 2.
An MBRS320, 20-V, 3-A diode in an SMC package is selected for both channels. This diode has a forward voltage drop of 0.4 V at 2 A.
The power dissipation in the diode is estimated by Equation 29.
For this design, the full load power dissipation is estimated to be 480 mW in D1, and 580 mW in D2.
The TPS54383's internal compensation limits the selection of the output capacitors. From Figure 25, the internal compensation has a double zero resonance at about 3 kHz. The output capacitor is selected by Equation 30.
Solving for COUT using
The resulting is COUT = 128 μF. The output ripple voltage of the converter is composed of the ripple voltage across the output capacitance and the ripple voltage across the ESR of the output capacitor. To find the maximum ESR allowable to meet the output ripple requirements the total ripple is partitioned, and the equation manipulated to find the ESR.
Based on 128 μF of capacitance, 300-kHz switching frequency and 50-mV ripple voltage plus rounding up the ripple current to 0.5 A, and the duty cycle to 50%, the capacitive portion of the ripple voltage is 6.5 mV, leaving a maximum allowable ESR of 87 mΩ.
To meet the ripple voltage requirements, a low-cost 100-μF electrolytic capacitor with 400 mΩ ESR (C5, C17) and two 10-μF ceramic capacitors (C3 and C4; and C18 and C19) with 2.5-mΩ ESR are selected. From the datasheets for the ceramic capacitors, the parallel combination provides an impedance of 28 mΩ @ 300 kHz for 14 mV of ripple.
The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 kΩ and 50 kΩ to maintain a balance between power dissipation and noise sensitivity. For this design, 20 kΩ is selected.
The lower resistors, R4 and R7 are found using the following equations.
Checking the ESR zero of the output capacitors:
where
Since the ESR zero of the main output capacitor is less than 20 kHz, an R-C filter is added in parallel with R4 and R7 to compensate for the electrolytic capacitors' ESR and add a zero approximately 40 kHz.
where
where
where
The TPS54383 datasheet recommends a minimum 10-μF ceramic input capacitor on each PVDD pin. These capacitor must be capable of handling the RMS ripple current of the converter. The RMS current in the input capacitors is estimated by Equation 38.
One 1210 10-μF, 25 V, X5R ceramic capacitor with 2-mΩ ESR and a 2-A RMS current rating are selected for each PVDD input. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to ensure the capacitors maintain sufficient capacitance at the working voltage.
To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 33-nF boot strap capacitor is used.
Current limit must be set above the peak inductor current IL(peak). Comparing IL(peak) to the available minimum current limits, ILIM is connected to BP for the highest current limit level.
The SEQ pin is left floating, leaving the enable pins to function independently. If the enable pins are tied together, the two supplies start-up ratiometrically. Alternatively, SEQ could be connected to BP or GND to provide sequential start-up.
The power dissipation in the TPS54383 is composed of FET conduction losses, switching losses and internal regulator losses. The RMS FET current is found using Equation 39.
This results in 1.05-A RMS for Channel 1 and 0.87-A RMS for Channel 2.
Conduction losses are estimated by:
Conduction losses of 198 mW and 136 mW are estimated for Channel 1 and Channel 2 respectively.
The switching losses are estimated in Equation 41.
From the data sheet of the MBRS320, the junction capacitance is 658 pF. Since this is large compared to the output capacitance of the TPS54x8x the FET capacitance is neglected, leaving switching losses of 17 mW for each channel.
The regulator losses are estimated in Equation 42.
With no external load on BP (IBP=0) the regulator power dissipation is 66 mW.
Total power dissipation in the device is the sum of conduction and switching for both channels plus regulator losses.
The total power dissipation is PDISS=0.198+0.136+0.017+0.017+.066 = 434 mW.
The following results are from the TPS54383-001 EVM.
For a higher input voltage, both a snubber and bootstrap resistors are added to reduce ringing on the switch node and a 30 V schottky diode is selected. A higher resistance feedback network is chosen for the 12 V output to reduce the feedback current.
PARAMETER | NOTES AND CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
VIN | Input voltage | 22 | 24 | 26 | V | |
OUTPUT CHARACTERISTICS | ||||||
VOUT1 | Output voltage 1 | VIN = nom, IOUT = nom | 12.0 | V | ||
VOUT2 | Output voltage 2 | VIN = nom, IOUT = nom | 5.0 | |||
IOUT1 | Output current 1 | VIN = min to max | 0 | 2.0 | A | |
IOUT2 | Output current 2 | VIN = min to max | 0 | 2.0 | ||
SYSTEM CHARACTERISTICS | ||||||
fSW | Switching frequency | 250 | 310 | 370 | kHz |
See the previous Detailed Design Procedure.
For a low input voltage application, the TPS54386 is selected for reduced size and all ceramic output capacitors are used. 22-μF input capacitors are selected to reduce input ripple and lead capacitors are placed in the feedback to boost phase margin.
PARAMETER | NOTES AND CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
VIN | Input voltage | 4.75 | 5 | 5.25 | V | |
OUTPUT CHARACTERISTICS | ||||||
VOUT1 | Output voltage 1 | VIN = nom, IOUT = nom | 1,2 | V | ||
VOUT2 | Output voltage 2 | VIN = nom, IOUT = nom | 3.3 | |||
IOUT1 | Output current 1 | VIN = min to max | 0 | 3 | A | |
IOUT2 | Output current 2 | VIN = min to max | 0 | 1 | ||
SYSTEM CHARACTERISTICS | ||||||
fSW | Switching frequency | 510 | 630 | 750 | kHz |
See the pervious Detailed Design Procedure and Using All Ceramic Output Capacitors.