SLUS829G August   2008  – February 2020 UCC2897A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Detailed Pin Descriptions
        1. 8.3.1.1  RDEL
        2. 8.3.1.2  RON
        3. 8.3.1.3  ROFF
        4. 8.3.1.4  VREF
        5. 8.3.1.5  SYNC
        6. 8.3.1.6  GND
        7. 8.3.1.7  CS
        8. 8.3.1.8  RSLOPE
        9. 8.3.1.9  FB
        10. 8.3.1.10 SS/SD
        11. 8.3.1.11 PGND
        12. 8.3.1.12 AUX
        13. 8.3.1.13 OUT
        14. 8.3.1.14 VDD
        15. 8.3.1.15 LINEUV
        16. 8.3.1.16 VIN
        17. 8.3.1.17 LINEOV
      2. 8.3.2 JFET Control and UVLO
      3. 8.3.3 Line Undervoltage Protection
      4. 8.3.4 Line Overvoltage Protection
      5. 8.3.5 Pulse Skipping
      6. 8.3.6 Synchronization
      7. 8.3.7 Gate Drive Connection
      8. 8.3.8 Bootstrap Biasing
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Oscillator
        2. 9.2.2.2 Soft Start
        3. 9.2.2.3 VDD Bypass Requirements
        4. 9.2.2.4 Delay Programming
        5. 9.2.2.5 Input Voltage Monitoring
        6. 9.2.2.6 Current Sense and Slope Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7.5 Electrical Characteristics

VDD = 12 V(1), 1-µF capacitor for VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RSLOPE = 50 kΩ, –40°C ≤ TA = TJ ≤ 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVERALL
ISTARTUP Start-up current VDD < VUVLO 300 500 µA
IDD Operating supply current(1)(2) VFB = 0 V,
VCS = 0V,
Outputs not switching		 2 3 mA
HIGH-VOLTAGE BIAS
IDD-ST VDD startup current Current available from VDD during startup, TA = –40°C to +85°C, VIN = 36 V(3) 4 11 mA
IVIN JFET leakage current VIN = 120 V; VDD = 14 V 75 µA
UNDERVOLTAGE LOCKOUT
UVLO Start threshold voltage 12.2 12.7 13.2 V
Minimum operating voltage after start 7.6 8 8.4
Hysteresis 4.4 4.7 5
LINE MONITOR
VLINEUV Line UV voltage threshold 1.243 1.268 1.294 V
ILINEUVHYS Line UV hysteresis current –11.5 –13 –14.5 µA
VLINEOV Line OV voltage threshold 1.243 1.268 1.294 V
ILINEOVHYS Line OV hysteresis current –11.5 –13 –14.5 µA
Soft-Start
ISSC SS charge current RON = 75 kΩ(4) –10.5 –14.5 –18.5 µA
ISSD SS discharge current RON = 75 kΩ(4) 10.5 14.5 18.5
VSS/SD Discharge/shutdown threshold voltage 0.4 0.5 0.6 V
VOLTAGE REFERENCE
VREF Reference voltage TJ = 25°C 4.85 5 5.15 V
VREF Reference voltage 0 A < IREF < 5 mA, over temperature 4.75 5 5.25
ISC Short circuit current REF = 0 V, TJ = 25°C –20 –11 –8 mA
INTERNAL SLOPE COMPENSATION
m Slope FB = High –10% RCS / RSLOPE +10%
OSCILLATOR
fOSC Oscillator frequency TJ = 25°C 237 250 265 kHZ
–40°C < TJ < 125°C; 8.5 V < VDD < 14.5 V 225 270
VP_P Oscillator amplitude (peak-to-peak) 2 V
SYNCHRONIZATION
SYNC input high voltage 3 V
SYNC input low voltage 1.6
SYNC pull down output current 600 µA
SYNC pull up output current –600
SYNC output pulse width 150 ns
tDEL SYNC-to-output delay 50
PWM(5)
DMAX Maximum duty cycle RON = ROFF = 75 kΩ, RDEL = 10 kΩ 66% 70% 74%
Minimum duty cycle 0%
PWM offset CS = 0 V 0.43 0.5 0.61 V
CURRENT SENSE
VLVL Current sense level shift voltage 0.4 0.5 0.6 V
VERR(max) Maximum voltage error (clamped) 5
VCS Current sense threshold cycle-by-cycle 0.43 0.48 0.53
OUTPUT (OUT AND AUX)
IOUT(src) Output source current –2 A
IOUT(sink) Output sink current 2
VOUT(low) Low-level output voltage IOUT = 150 mA 0.4 V
VOUT(high) High-level output voltage IOUT = –150 mA 11.1
(1) Set VDD above the start threshold before setting at 12 V.
(2) Does not include current of the external oscillator network.
(3) The power supply starts with IDD–ST load on VDD, the part starts up with no load up to 125°C. For more information see the section for VIN and VDD
(4) ISSC and ISS/SD are directly proportional to IRON. See Equation 8.
(5) Maximum pulse width needs to be less than DMAX, which is a function of RON and ROFF. For more information on DMAX, see detailed description for ROFF in .