SLUSAB0D October   2010  – April 2016 BQ24153A , BQ24156A , BQ24158 , BQ24159

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparisons
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage Protection
        1. 9.3.1.1 Input Overvoltage Protection
        2. 9.3.1.2 Bad Adaptor Detection/Rejection
        3. 9.3.1.3 Sleep Mode
        4. 9.3.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)
      2. 9.3.2 Battery Protection
        1. 9.3.2.1 Output Overvoltage Protection
        2. 9.3.2.2 Battery Short Protection
        3. 9.3.2.3 Battery Detection at Power Up in 15-minute Mode (bq24153A/6A only)
        4. 9.3.2.4 Battery Detection in Host Mode
      3. 9.3.3 15-Minute Safety Timer and 32-second Watchdog Timer in Charge Mode
      4. 9.3.4 USB Friendly Power Up
      5. 9.3.5 Input Current Limiting at Power Up
    4. 9.4 Device Functional Modes
      1. 9.4.1 Charge Mode Operation
        1. 9.4.1.1 Charge Profile
      2. 9.4.2 PWM Controller in Charge Mode
      3. 9.4.3 Battery Charging Process
      4. 9.4.4 Thermal Regulation and Protection
      5. 9.4.5 Charge Status Output, STAT Pin
      6. 9.4.6 Control Bits in Charge Mode
        1. 9.4.6.1 CE Bit (Charge Mode)
        2. 9.4.6.2 RESET Bit
        3. 9.4.6.3 OPA_Mode Bit
      7. 9.4.7 Control Pins in Charge Mode
        1. 9.4.7.1 CD Pin (Charge Disable)
        2. 9.4.7.2 SLRST Pin (Safety Limit Register 06H Reset, bq24156A/9 only)
      8. 9.4.8 BOOST Mode Operation (bq24153A/8 only)
        1. 9.4.8.1 PWM Controller in Boost Mode
        2. 9.4.8.2 Boost Start Up
        3. 9.4.8.3 PFM Mode at Light Load
        4. 9.4.8.4 Safety Timer in Boost Mode
        5. 9.4.8.5 Protection in Boost Mode
          1. 9.4.8.5.1 Output Overvoltage Protection
          2. 9.4.8.5.2 Output Overload Protection
          3. 9.4.8.5.3 Battery Overvoltage Protection
        6. 9.4.8.6 STAT Pin in Boost Mode
      9. 9.4.9 High Impedance (HI-Z) Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
        1. 9.5.1.1 F/S Mode Protocol
        2. 9.5.1.2 H/S Mode Protocol
        3. 9.5.1.3 I2C Update Sequence
        4. 9.5.1.4 Slave Address Byte
        5. 9.5.1.5 Register Address Byte
    6. 9.6 Register Maps
      1. 9.6.1 Status/Control Register [Memory Location: 00, Reset State: x1xx 0xxx]
      2. 9.6.2 Control Register [Memory Location: 01, Reset State: 0011 0000]
      3. 9.6.3 Control/Battery Voltage Register [Memory Location: 02, Reset State: 0000 1010]
      4. 9.6.4 Vender/Part/Revision Register [Memory Location: 03, Reset State: 0101 000x]
      5. 9.6.5 Battery Termination/Fast Charge Current Register [Memory Location: 04, Reset State: 0000 000]
      6. 9.6.6 Special Charger Voltage/Enable Pin Status Register [Memory location: 05, Reset state: 001X X100]
      7. 9.6.7 Safety Limit Register [Memory location: 06, Reset state: 01000000]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Systems Design Specifications
        2. 10.2.2.2 Charge Current Sensing Resistor Selection Guidelines
        3. 10.2.2.3 Output Inductor and Capacitance Selection Guidelines
      3. 10.2.3 Application Curves
    3. 10.3 System Example
  11. 11Power Supply Recommendations
    1. 11.1 System Load After Sensing Resistor
    2. 11.2 System Load Before Sensing Resistor
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Current Path
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Summary
      1. 14.1.1 Chip Scale Packaging Dimensions

11 Power Supply Recommendations

11.1 System Load After Sensing Resistor

One of the simpler high-efficiency topologies connects the system load directly across the battery pack, as shown in Figure 37. The input voltage has been converted to a usable system voltage with good efficiency from the input. When the input power is on, it supplies the system load and charges the battery pack at the same time. When the input power is off, the battery pack powers the system directly.

bq24153A bq24156A bq24158 bq24159 syslda_lusa27.gif Figure 37. System Load After Sensing Resistor

The advantages of system load after sensing resistor:

  1. When the AC adapter is disconnected, the battery pack powers the system load with minimum power dissipation. Consequently, the time that the system runs on the battery pack can be maximized.
  2. It reduces the number of external path selection components and offers a low-cost solution.
  3. Dynamic power management (DPM) can be achieved. The total of the charge current and the system current can be limited to a desired value by setting the charge current value. When the system current increases, the charge current drops by the same amount. As a result, no potential over-current or over-heating issues are caused by excessive system load demand.
  4. The total input current can be limited to a desired value by setting the input current limit value. USB specifications can be met easily.
  5. The supply voltage variation range for the system can be minimized.
  6. The input current soft-start can be achieved by the generic soft-start feature of the IC.

Design considerations and potential issues:

  1. If the system always demands a high current (but lower than the regulation current), the battery charging never terminates. Thus, the battery is always charged, and its lifetime may be reduced.
  2. Because the total current regulation threshold is fixed and the system always demands some current, the battery may not be charged with a full-charge rate and thus may lead to a longer charge time.
  3. If the system load current is large after the charger has been terminated, the IR drop across the battery impedance may cause the battery voltage to drop below the refresh threshold and start a new charge cycle. The charger would then terminate due to low charge current. Therefore, the charger would cycle between charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold, resulting in a much slower cycling.
  4. In a charger system, the charge current is typically limited to about 30mA, if the sensed battery voltage is below 2V short circuit protection threshold. This results in low power availability at the system bus. If an external supply is connected and the battery is deeply discharged, below the short circuit protection threshold, the charge current is clamped to the short circuit current limit. This then is the current available to the system during the power-up phase. Most systems cannot function with such limited supply current, and the battery supplements the additional power required by the system. Note that the battery pack is already at the depleted condition, and it discharges further until the battery protector opens, resulting in a system shutdown.
  5. If the battery is below the short circuit threshold and the system requires a bias current budget lower than the short circuit current limit, the end-equipment will be operational, but the charging process can be affected depending on the current left to charge the battery pack. Under extreme conditions, the system current is close to the short circuit current levels and the battery may not reach the fast-charge region in a timely manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process. Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the application possible.
  6. If the battery pack voltage is too low, highly depleted, totally dead or even shorted, the system voltage is clamped by the battery and it cannot operate even if the input power is on.

11.2 System Load Before Sensing Resistor

The second circuit is similar to first one; the difference is that the system load is connected before the sense resistor, as shown in Figure 38.

bq24153A bq24156A bq24158 bq24159 sysldb_lusa27.gif Figure 38. System Load Before Sensing Resistor

The advantages of system load before sensing resistor to system load after sensing resistor:

  1. The charger controller is based only on the current going through the current-sense resistor. So, the constant current fast charge and termination functions operate without being affected by the system load. This is the major advantage of having the system load connected before the sense resistor.
  2. A depleted battery pack can be connected to the charger without the risk of the safety timer expiration caused by high system load.
  3. The charger can disable termination and keep the converter running to keep battery fully charged; or let the switcher terminate when the battery is full and then allow the system to run off of the battery through the sense resistor.

Design considerations and potential issues:

  1. The total current is limited by the IC input current limit, or peak current protection, but not the charge current setting. The charge current does not drop when the system current load increases until the input current limit is reached. This solution is not recommended if the system requires a high current.
  2. Efficiency declines when discharging through the sense resistor to the system.
  3. No thermal regulation. Therefore, the system design should ensure the maximum junction temperature of the IC is below 125°C during normal operation.