SLUSCD1C June   2017  – November 2018 TPS2373

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD Auxiliary Power Detect
      2. 7.3.2  PG Power Good (Converter Enable) Pin Interface
      3. 7.3.3  CLSA and CLSB Classification
      4. 7.3.4  DEN Detection and Enable
      5. 7.3.5  Internal Pass MOSFET
      6. 7.3.6  TPH, TPL and BT PSE Type Indicators
      7. 7.3.7  VC_IN, VC_OUT, UVLO_SEL, and Advanced PWM Startup
      8. 7.3.8  AMPS_CTL, MPS_DUTY and Automatic MPS
      9. 7.3.9  VDD Supply Voltage
      10. 7.3.10 VSS
      11. 7.3.11 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1  PoE Overview
      2. 7.4.2  Threshold Voltages
      3. 7.4.3  PoE Startup Sequence
      4. 7.4.4  Detection
      5. 7.4.5  Hardware Classification
      6. 7.4.6  Inrush and Startup
      7. 7.4.7  Maintain Power Signature
      8. 7.4.8  Advanced Startup and Converter Operation
      9. 7.4.9  PD Hotswap Operation
      10. 7.4.10 Startup and Power Management, PG and TPH, TPL, BT
      11. 7.4.11 Adapter ORing
      12. 7.4.12 Using DEN to Disable PoE
      13. 7.4.13 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Requirements
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistors, RCLSA and RCLSB
        6. 8.2.2.6  APD Pin Divider Network RAPD1, RAPD2
        7. 8.2.2.7  Opto-isolators for TPH, TPL and BT
        8. 8.2.2.8  VC Input and Output, CVCIN and CVCOUT
        9. 8.2.2.9  UVLO Select, UVLO_SEL
        10. 8.2.2.10 Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
        11. 8.2.2.11 Internal Voltage Reference, RREF
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 EMI Containment
    4. 10.4 Thermal Considerations and OTSD
    5. 10.5 ESD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.4.6 Inrush and Startup

IEEE 802.3bt has a startup current and time limitation, providing compatibility between a PSE of any Type and a PD of any Type. The PSE inrush limit varies according to the allotted power. If Class 0 to 4, Class 5 to 6 or Class 7 to 8, the inrush limit is respectively from 400 mA to 450 mA, 400 mA to 900 mA or 800 mA to 900 mA. PSE inrush limit applies for up to 75 ms after power up (applying "48 V" to the PI), after which the Type 2, 3, or 4 PSE will support a higher output current in accordance with the allocated class. The TPS2373-3 and TPS2373-4 respectively implement a 200-mA and 335-mA inrush current, which is compatible with all PSE Types. A high-power PD must limit its converter startup peak current. The operational current for Type 2 and 3, and preferably Type 4, cannot exceed 400 mA for a period of 80 ms.