The UVLO circuit ensures that V_CC is adequate to make the UC1843B-SP fully operational before enabling the output stage. Figure 7-4 shows that the UVLO turnon and turnoff thresholds are fixed internally at 8.4 V and 7.6 V, respectively. The 0.6-V hysteresis prevents V_CC oscillations during power sequencing.

Figure 7-5 shows supply current requirements. Start-up current is < 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as shown in Figure 7-6. During normal circuit operation, V_CC is developed from auxiliary winding, W_Aux, with D₁ and C_IN. However, at start-up, C_IN must be charged to 8.4 V through R_IN. With a start-up current of 1 mA, R_IN can be as large as 100 kΩ and still charge C_IN when V_AC = 90-V RMS (low line). Power dissipation in R_IN would then be less than 350 mW even under high line (V_AC = 130-V RMS) conditions.

During UVLO, the output driver is in a low state. While it does not exhibit the same saturation characteristics as normal operation, it can easily sink 1 mA, enough to ensure the MOSFET is held off. For efficient operations, an LDO can take the place of R_IN and be disabled during the operation of the device.

Figure 7-4 UVLO Turnon and Turnoff Threshold

During UVLO, the output driver is biased to sink minor amounts of current.

Figure 7-5 Supply Current Requirements

Figure 7-6 Providing Power to the UC1843B-SP