SLUSDG1C
June 2020 ā August 2022
BQ25792
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Description (continued)
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Device Power-On-Reset
9.3.2
PROG Pin Configuration
9.3.3
Device Power Up from Battery without Input Source
9.3.4
Device Power Up from Input Source
9.3.4.1
Power Up REGN LDO
9.3.4.2
Poor Source Qualification
9.3.4.3
ILIM_HIZ Pin
9.3.4.4
Default VINDPM Setting
9.3.4.5
Input Source Type Detection
9.3.4.5.1
D+/Dā Detection Sets Input Current Limit
9.3.4.5.2
HVDCP Detection Procedure
9.3.4.5.3
Connector Fault Detection
9.3.5
Dual-Input Power Mux
9.3.5.1
ACDRV Turn On Condition
9.3.5.2
VBUS Input Only
9.3.5.3
One ACFET-RBFET
9.3.5.4
Two ACFETs-RBFETs
9.3.6
Buck-Boost Converter Operation
9.3.6.1
Force Input Current Limit Detection
9.3.6.2
Input Current Optimizer (ICO)
9.3.6.3
Pulse Frequency Modulation (PFM)
9.3.6.4
Device HIZ State
9.3.7
USB On-The-Go (OTG)
9.3.7.1
OTG Mode to Power External Devices
9.3.8
Power Path Management
9.3.8.1
Narrow VDC Architecture
9.3.8.2
Dynamic Power Management
9.3.9
Battery Charging Management
9.3.9.1
Autonomous Charging Cycle
9.3.9.2
Battery Charging Profile
9.3.9.3
Charging Termination
9.3.9.4
Charging Safety Timer
9.3.9.5
Thermistor Qualification
9.3.9.5.1
JEITA Guideline Compliance in Charge Mode
9.3.9.5.2
Cold/Hot Temperature Window in OTG Mode
9.3.10
Integrated 16-Bit ADC for Monitoring
9.3.11
Status Outputs ( STAT, and INT)
9.3.11.1
Charging Status Indicator (STAT Pin)
9.3.11.2
Interrupt to Host ( INT)
9.3.12
Ship FET Control
9.3.12.1
Shutdown Mode
9.3.12.2
Ship Mode
9.3.12.3
System Power Reset
9.3.13
Protections
9.3.13.1
Voltage and Current Monitoring
9.3.13.2
Thermal Regulation and Thermal Shutdown
9.3.14
Serial Interface
9.3.14.1
Data Validity
9.3.14.2
START and STOP Conditions
9.3.14.3
Byte Format
9.3.14.4
Acknowledge (ACK) and Not Acknowledge (NACK)
9.3.14.5
Target Address and Data Direction Bit
9.3.14.6
Single Write and Read
9.3.14.7
Multi-Write and Multi-Read
9.4
Device Functional Modes
9.4.1
Host Mode and Default Mode
9.4.2
Register Bit Reset
9.5
Register Map
9.5.1
I2C Registers
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Inductor Selection
10.2.2.2
Input (VBUS / PMID) Capacitor
10.2.2.3
Output (VSYS) Capacitor
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Third-Party Products Disclaimer
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Receiving Notification of Documentation Updates
13.4
Support Resources
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
13.2
Documentation Support