SLUSDK4 Data sheet

SLUSDK4E may 2020 – july 2023 UCC28782

PRODUCTION DATA

7.5 Electrical Characteristics

Unless otherwise stated: V_VDD = 20 V, V_BIN = 20 V, R_RDM = 115 kΩ, R_RTZ = 140 kΩ, V_BUR = 1.2 V, V_SET = 0 V, R_NTC = 50 kΩ, V_VS = 4 V, V_SWS = 0 V, I_FB = 0 μA, C_PWML = 0 pF, C_PWMH = 0 pF, C_REF = 0.22 µF, C_P13 = 1 µF, and -40⁰C < T_J = T_A < 125⁰C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VDD INPUT
I_RUN(STOP)	Supply current, run state	No switching	0.88	2.2	2.66	mA
I_RUN(SW)	Supply current, run state	Switching, I_VSL = 0 µA	2.66	3	3.55	mA
I_WAIT	Supply current, wait state	I_FB = -85 µA, V_BIN = V_BSW = V_VDD = 20 V, sum of I_BIN, I_BSW, and I_VDD	452	580	695	µA
I_WAIT	Supply current, wait state	I_FB = -85 µA, BIN and BSW pins to AGND, I_VDD only	465	540	658	µA
I_START	Supply current, start state	V_VDD = V_VDD(ON) - 100 mV, V_VS = 0 V	150	235	301	µA
I_FAULT	Supply current, fault state	fault state		500	630	µA
I_VDD(LIMIT)	VDD startup current limit during startup	V_VDD increasing, V_SWS - V_VDD = 1 V, V_VDD = 16.5 V	1.2	2	2.53	mA
V_VDD(ON)	VDD turnon threshold	V_VDD increasing	16.31	17	17.91	V
V_VDD(OFF)	VDD turnoff threshold	V_VDD decreasing	9.94	10.6	11.17	V
V_VDD(PCT)	Offset to power cycle for long output voltage overshoot	Offset above V_VDD(OFF), I_FB = -85 µA	1.54	2.2	2.98	V
V_VDD(RST)	Logic reset threshold for latched fault	Voltage that VDD must cross H-L to reset a latched-off fault condition	3.3	4.3	4.61	V
V_VDD(BOOST)	VDD regulation level in boost mode	I_VDD = 0 mA to 30 mA, V_BIN = 9 V	17.6	18.5	19.4	V
BIN INPUT
V_BIN(ON)	UVLO on voltage of V_BIN in boost mode	V_BIN increasing	2.03	2.2	2.42	V
V_BIN(OFF)	UVLO hysteresis below V_BIN(ON) in boost mode	V_BIN decreasing	1.13	1.23	1.33	V
V_BIN(EN)	Highest V_BIN to enable boost mode	V_BIN decreasing	14.44	14.9	15.47	V
V_BIN(DIS)	Hysteresis above V_BIN(EN) to disable boost mode	V_BIN increasing	0.12	0.16	0.18	V
BSW INPUT
R_BSW	R_DS(on) of internal boost switch		0.94	1.4	2.28	Ω
I_BSW(MAX)	Peak current threshold in CPC control		0.27	0.335	0.38	A
t_BLEB	Leading edge blanking time in boost mode		129	190	247	ns
f_BSW	Maximum switching frequency in CPC control, for UCC28782A only	V_BIN = 9 V	389	420	467	kHz
f_BSW	Maximum switching frequency in CPC control, for UCC28782AD, UCC28782BDL, and UCC28782CD only	V_BIN = 9 V	389	420	499	kHz
t_BOFF(MIN)	Minimum off time in COT control	I_FB = -85 µA	198	255	353	ns
t_BOFF(MIN)	Minimum off time in COT control	I_BSW = 500 mA	2.9	4.35	5.9	μs
P13 OUTPUT
V_P13	P13 voltage level including load regulation	0 mA to 60 mA out of P13, run state, V_VDD = 20 V	12.0	12.8	13.6	V
I_P13(START)	Max sink current of P13 pin during startup	V_P13 = 14 V	1.53	2.2	3.04	mA
I_P13(MAX)	Current sourcing limit of P13 pin	P13 shorted to AGND, V_VDD = 20 V	103.3	133	154.5	mA
VR13_(LINE)	Line regulation of V_P13	V_VDD = 15 V to 35 V	-6	2	8.7	mV
V_P13(OV)	Over voltage fault threshold above V_P13		1.35	2	2.54	V
R_P13	Dropout resistance of P13 regulator switch between VDD and P13 pins	(V_VDD - V_P13) / 30 mA, V_VDD = 11 V, 30 mA out of P13	8.5	13	22.7	Ω
S13 OUTPUT
R_S13	R_DS(on) of internal disconnect switch between P13 and S13 pins	(V_P13 - V_S13) / 30 mA, V_VDD = 11 V, 30 mA out of S13	2.1	2.8	3.82	Ω
V_{S13_OK}	S13_OK threshold to enable switching	V_RUN = 5 V	9.63	10.2	10.7	V
I_S13(MAX)	Current sourcing limit of S13 pin	S13 shorted to AGND, V_VDD = 20 V	260.7	350	452.5	mA
REF OUTPUT
V_REF	REF voltage level	I_REF = 0 A	4.9	5	5.13	V
I_REF(MAX)	Current sourcing limit of REF pin	REF shorted to AGND, V_VDD = 20 V	14.3	17	20.3	mA
VR5_(LINE)	Line regulation of V_REF	V_VDD = 12 V to 35 V	-7	-3	1	mV
VR5_(LOAD)	Load regulation of V_REF	0 mA to 1 mA out of REF, change in V_REF	-16	0.1	25	mV
VS INPUT
V_VSNC	Negative clamp level	I_VSL = -1.25 mA, voltage below ground	221	287	344	mV
V_ZCD	Zero-crossing detection (ZCD) level	V_VS decreasing	12.4	35	67.2	mV
I_VSB	Input bias current	V_VS = 4 V	-0.23	0	0.31	µA
V_VS(SM1)	VS threshold voltage in SM1 startup mode		242.4	282	318.3	mV
V_VS(SM2)	VS threshold voltage in SM2 startup mode		458.3	500	543	mV
V_VSLV(UP)	VS upper threshold out of low output voltage mode (LV mode)	V_VS increasing	2.41	2.49	2.6	V
V_VSLV(LR)	VS lower threshold into low output voltage mode (LV mode)	V_VS decreasing	2.3	2.39	2.49	V
t_ZC	Zero-crossing timeout delay		1.95	2.3	2.73	µs
t_D(ZCD)	Propagation delay from ZCD high to PWML 10 % high	V_VS step from 4 V to -0.1 V	23	50	81	ns
CS INPUT
V_CST(MAX)	Peak-power threshold on CS pin out of LV mode	I_VSL = 0 μA, V_VS ≥ V_VSLV(UP)	767.4	801	836.4	mV
		I_VSL = -333 μA, V_VS ≥ V_VSLV(UP)	650	727	788.7	mV
		I_VSL = -666 μA, V_VS ≥ V_VSLV(UP)	570	600	651.8	mV
		I_VSL = -1.25 mA, V_VS ≥ V_VSLV(UP)	537.2	570	612	mV
V_{CST(MAX)_LV}	Peak-power threshold on CS pin in LV mode	I_VSL = 0 mA, V_VS ≤ V_VSLV(LR)	593.7	628	663.9	mV
		I_VSL = -666 μA, V_VS ≤ V_VSLV(LR)	546	570	609.5	mV
		I_VSL = -1.25 mA, V_VS ≤ V_VSLV(LR)	511.2	540	584.7	mV
V_CST(MIN)	Minimum CS threshold voltage	V_CS increasing, I_FB = -85 µA	120.7	153	200.1	mV
K_LC	Line-compensation current ratio	I_VSL = -1.25 mA, I_VSL / current out of CS pin	21.6	25	29	A/A
V_CST(EMI)⁽¹⁾	EMI dithering magnitude on CS pin out of LV mode	(V_BUR / K_BUR-CST) < V_CST < V_CST(MAX), I_VSL < -646 μA, V_VS ≥ V_VSLV(UP)	78.4	96	113.6	mV
V_{CST(EMI)_LV}⁽¹⁾	EMI dithering magnitude on CS pin in LV mode	(V_BUR / K_BUR-CST) < V_CST < V_CST(MAX), I_VSL < -646 μA, V_VS ≤ V_VSLV(LR)	29.3	36	42.7	mV
V_CST(SM1)	CS threshold voltage in SM1 startup mode	V_VS < V_VS(SM1)	177.5	200	222.9	mV
V_CST(SM2)	CS threshold voltage in SM2 startup mode	V_VS < V_VS(SM2)	470.4	500	531.4	mV
t_CSLEB	Leading-edge-blanking time	V_SET = 5 V, V_CS = 1 V	171.2	190	216.1	ns
t_CSLEB	Leading-edge-blanking time	V_SET = 0 V, V_CS = 1 V	94.4	108	125	ns
t_D(CS)	Propagation delay of CS comparator high to PWML 90 % low	V_CS step from 0 V to 1 V	10	26	34.8	ns
f_DITHER⁽¹⁾	EMI dithering frequency on CS pin	(V_BUR / K_BUR-CST) < V_CST < V_CST(OPP), I_VSL < -646 μA	20	23	27	kHz
BUR INPUT and Low-power MODE
K_BUR-CST	Ratio of V_BUR to V_CST	V_BUR between 0.7 V and 2.4 V	3.82	3.98	4.09	V/V
I_BUR(LPM)	Bias source current of V_BUR offset in LPM		2.09	2.65	3.16	µA
I_BUR(AAM)	Bias sink current of V_BUR offset in AAM	V_CST > V_BUR / K_BUR-CST	3.76	4.85	5.81	µA
f_BUR(UP1)	First upper threshold of burst frequency in ABM		30.7	34.4	38.5	kHz
f_BUR(UP2)	Second upper threshold of burst frequency in ABM	V_VS = 2.2 V	41.8	51.2	58.9	kHz
f_BUR(LR)	Lower threshold of burst frequency in ABM		21.3	24.5	28.1	kHz
f_LPM	Burst frequency in low-power mode		23.3	25	26.9	kHz
IPC INPUT and SBP2 MODE
V_{CST_IPC(UP)}	Highest programmable V_CST range of SBP2 by IPC pin	V_IPC = 5 V	373.8	405	438.5	mV
K_IPC	Ratio of the programmable IPC voltage to V_CST	V_IPC between 1.8 V and 3.8 V	59.3	64	68.4	mV/V
V_{CST_IPC(LR)}	Lowest programmable V_CST range of SBP2 by IPC pin	V_IPC = 1 V	247.5	273	307.7	mV
V_{CST_IPC(MIN)}	Minimum V_CST of SBP2 by grounding IPC pin	V_IPC = 0 V	128.1	154	191.5	mV
I_IPC(SBP2)	Bias source current of V_IPC offset in SBP2	I_FB = -85 µA	40.7	49	55.7	µA
f_SBP2(UP)	Upper threshold of burst frequency in SBP2		6	8.5	13.4	kHz
f_SBP2(LR)	Lower threshold of burst frequency in SBP2	V_IPC = 2 V	1	1.7	2	kHz
RUN
V_RUNH	RUN pin high-level	I_RUN = -0.2 mA	4.6	4.78	5	V
V_RUNL	RUN pin low-level, for UCC28782A only	I_RUN = 1 mA	0.23	0.25	0.3	V
V_RUNL	RUN pin low-level, for UCC28782AD, UCC28782BDL, and UCC28782CD only	I_RUN = 1 mA	0.1	0.25	0.3	V
I_SRC(RUN)	RUN peak source current	V_RUN= 2.3 V	33	44	52	mA
I_SRC(RUN)	RUN peak source current	V_RUN= 3 V	14	20	25	mA
t_R(RUN)	Turn-on rise time of RUN, from 0 V to 2.5 V	C_RUN = 22 nF, V_RUN from 0 V to 2.5 V	0.4	0.79	1	µs
t_F(RUN)	Turn-off fall time of RUN, 90 % to 10 %	C_RUN = 10 pF		20	32	ns
PWML
V_PWMLH	PWML pin high-level	I_PWML = -1 mA	12.1	12.85	13.6	V
V_PWMLL	PWML pin low-level	I_PWML = 1 mA		0.002	0.1	V
I_SRC(PWML)⁽¹⁾	PWML peak source current	V_PWML = 0 V	0.25	0.5	0.8	A
I_SNK(PWML)⁽¹⁾	PWML peak sink current	V_PWML = 13 V	1.2	1.9	2.8	A
R_SRC(PWML)	PWML pull-up resistance	I_PWML = -20 mA	3.1	4.3	6.1	Ω
R_SNK(PWML)	PWML pull-down resistance	I_PWML = 20 mA	0.5	1.1	1.9	Ω
t_R(PWML)	Turn-on rise time of PWML, 10 % to 90 %	C_PWML = 1.5 nF		30	53	ns
t_F(PWML)	Turn-off fall time of PWML, 90 % to 10 %	C_PWML = 1.5 nF		9	20	ns
t_D(RUN-PWML)	Delay from RUN high to PWML high	V_S13 > 11 V	1.92	4.7	7.43	µs
t_ON(MIN)	Minimum on-time of PWML in LPM, for UCC28782A only	V_SET = 5 V, I_FB = -85 µA, V_CS= 1 V	68	105	172.5	ns
t_ON(MIN)	Minimum on-time of PWML in LPM, for UCC28782AD, UCC28782BDL, and UCC28782CD only	V_SET = 5 V, I_FB = -85 µA, V_CS= 1 V	68	105	175	ns
PWMH
V_PWMHH	PWMH pin high-level	I_PWMH = -1 mA	4.39	4.66	4.83	V
V_PWMHL	PWMH pin low-level, for UCC28782A only	I_PWMH = 1 mA	0.19	0.198	0.21	V
V_PWMHL	PWMH pin low-level, for UCC28782AD, UCC28782BDL, and UCC28782CD only	I_PWMH = 1 mA	0.1	0.198	0.21	V
I_SRC(PWMH)	PWMH peak source current	V_PWMH = 2.5 V	16.5	21	26.2	mA
I_SRC(PWMH)	PWMH peak source current	V_PWMH = 3.5 V	3.8	6	7.6	mA
t_R(PWMH)	Turn-on rise time of PWMH, 10 % to 90 %, for UCC28782A only	C_PWMH = 10 pF		8	20	ns
t_R(PWMH)	Turn-on rise time of PWMH, 10 % to 90 %, for UCC28782AD, UCC28782BDL, and UCC28782CD only	C_PWMH = 10 pF		8	24	ns
t_F(PWMH)	Turn-off fall time of PWMH, 90 % to 10 %	C_PWMH = 10 pF		22	29	ns
t_D(VS-PWMH)	Dead time between VS high and PWMH 10 % high		10	18	28	ns
PROTECTION
V_OVP	Over-voltage threshold	V_VS increasing	4.4	4.55	4.67	V
V_OCP	Over-current threshold	V_CS increasing	1.14	1.22	1.27	V
K_OPP-PPL	Ratio of over-power threshold to peak-power threshold	V_CST(OPP) / V_CST(MAX) , and V_{CST(OPP)_LV}/ V_{CST(MAX)_LV}	0.72	0.75	0.78	V/V
I_VSL(RUN)	VS line-sense run current	Current out of VS pin increasing	313	365	408.6	µA
I_VSL(STOP)	VS line-sense stop current	Current out of VS pin decreasing	255	305	336.4	µA
K_VSL	VS line sense ratio	I_VSL(STOP) / I_VSL(RUN)	0.72	0.836	0.9	A/A
R_RDM(TH)	R_RDM threshold for CS pin fault		35	55	70	kΩ
T_J(STOP)	Thermal-shutdown temperature	Internal junction temperature	125	162		°C
V_BOVPTH	Shut-down voltage of V_VDD for boost output OVP		21.5	25	28.2	V
V_BOVPR	Recovery voltage of V_VDD for boost output OVP		16.8	20	23.3	V
t_OPP	OPP fault timer, for UCC28782A only	I_FB = 0 A	133.3	164	201.1	ms
t_OPP	OPP fault timer, for UCC28782AD, UCC28782BDL, and UCC28782CD only	I_FB = 0 A	130	164	201.1	ms
t_BO	Brown-out detection delay time	I_VSL < I_VSL(STOP)	28.8	55	85.2	ms
t_CSF1	Maximum PWML on-time for detecting CS pin fault	V_SET = 5 V	1.6	2.05	2.5	µs
t_CSF0	Maximum PWML on-time for detecting CS pin fault	R_RDM < R_RDM(TH) for V_SET = 0 V	0.85	1.05	1.27	µs
t_FDR	Fault reset delay timer, for UCC28782A only	OCP, OPP, OVP, SCP or CS pin fault	1.2	1.5	2.22	s
t_FDR	Fault reset delay timer, for UCC28782AD, UCC28782BDL, and UCC28782CD only	OCP, OPP, OVP, SCP or CS pin fault	1.2	1.5	2.25	s
FLT INPUT
V_NTCTH	NTC shut-down voltage	FLT voltage decreasing	0.47	0.5	0.52	V
R_NTCTH	NTC shut-down resistance	R_NTC decreasing	8.9	9.91	11.18	kΩ
R_NTCR	NTC recovery resistance	R_NTC increasing	21.2	23	26.4	kΩ
I_FLT	Input bias current for V_FLT at V_IOVPTH	V_FLT = 4.5 V	-0.1	0	0.1	µA
V_IOVPTH	Shut-down voltage of input OVP	FLT voltage increasing	4.3	4.5	4.67	V
V_IOVPR	Hysteresis of input OVP	FLT voltage increasing	57.7	74	87	mV
t_FLT(NTC)	Delay time of NTC fault		14	50	100	µs
t_FLT(IOVP)	Delay time of input OVP fault		555	750	917	µs
V_FLTZ	Clamp voltage of FLT pin	I_FLT = 150 µA	5.08	5.5	5.61	V
RTZ INPUT
K_TZ	t_Z compensation ratio	Ratio of t_Z at I_VSL = -200 µA to t_Z at I_VSL = -733 µA	1.27	1.41	1.54	s/s
t_Z(MAX)	Maximum programmable dead time from PWMH low to PWML high	R_RTZ = 280 kΩ, I_VSL = -1 mA, V_SET = 5 V	397.8	478	592.8	ns
t_Z(MIN)	Minimum programmable dead time from PWMH low to PWML high	R_RTZ = 78.4 kΩ, I_VSL = -1 mA, V_SET = 0 V	56.1	70	89.1	ns
t_Z	Dead time from PWMH low to PWML high	I_VSL = -200 µA	152.2	175	212.7	ns
		I_VSL = -450 µA	129.2	150	190	ns
		I_VSL = -733 µA	109.7	125	147.2	ns
SWS INPUT
V_TH(SWS)	SWS zero voltage threshold	V_SET = 5 V	8.1	8.5	9.1	V
V_TH(SWS)	SWS zero voltage threshold	V_SET = 0 V	3.7	4.04	4.4	V
t_D(SWS-PWML)	Time between SWS low to PWML 10 % high	V_SWS step from 5 V to 0 V	11.4	17	24.8	ns
FB INPUT
I_FB(SBP)	Maximum control FB current	I_FB increasing	64.2	75	87.1	µA
V_FB(REG)	Regulated FB voltage level		4.02	4.25	4.53	V
R_FBI	FB input resistance		7.5	8.3	9.6	kΩ
dI_COMP/dt⁽¹⁾	Slope of internal ramp compensation current		0.192	0.214	0.236	A/s
I_COMP	Magnitude of internal ramp compensation current		4	6.75	8	µA
RDM INPUT
t_DM(MAX)	Maximum PWMH width with maximum tuning, for UCC28782A only	V_SWS = 12 V	6.32	6.95	7.53	µs
t_DM(MAX)	Maximum PWMH width with maximum tuning, for UCC28782AD, UCC28782BDL, and UCC28782CD only	V_SWS = 12 V	6.0	6.95	7.53	µs
t_DM(MIN)	Minimum PWMH width with minimum tuning, for UCC28782A only	V_SWS = 0 V	3.11	3.43	3.77	µs
t_DM(MIN)	Minimum PWMH width with minimum tuning, for UCC28782AD, UCC28782BDL, and UCC28782CD only	V_SWS = 0 V	3.0	3.43	3.77	µs
XCD INPUT (for UCC28782AD, UCC28782BDL, and UCC28782CD only)
V_XCD(LR)	XCD lower zero-crossing threshold		5.9	6.62	7.2	V
V_XCD(UP)	XCD upper zero-crossing threshold		6.8	7.5	7.9	V
I_XCD(0)	Leakage current in XCD wait state	V_XCD = 15 V		0.3	1.7	µA
I_XCD(1)	First-step XCD sense current	V_XCD = 15 V	0.32	0.4	0.46	mA
I_XCD(2)	Second-step XCD sense current	V_XCD = 15 V	0.61	0.775	0.91	mA
I_XCD(3)	Third-step XCD sense current	V_XCD = 15 V	0.73	1.15	1.6	mA
I_XCD(4)	Fourth-step XCD sense current	V_XCD = 15 V	1.2	1.53	1.81	mA
I_XCD(MAX)	Maximum XCD discharge current	V_XCD = 15 V	1.65	2	2.5	mA
V_XCD(OVP)	Clamping voltage for XCD OVP	I_XCD = 20 mA	23	26	30	V
t_XCD(STEP)	Dwell time for each XCD sense step, for UCC28782A only		10	12	14	ms
t_XCD(STEP)	Dwell time for each XCD sense step, for UCC28782AD, UCC28782BDL, and UCC28782CD only		9	12	14	ms
t_XCD(MAX)	Maximum XCD discharge time		230.4	300	373.3	ms
t_XCD(WAIT)	XCD wait time			700	1071	ms

(1) Ensured by design, not tested in production