SLUSDO1B
june 2019 – august 2023
BQ25155
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Key Default Settings
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Linear Charger and Power Path
9.3.1.1
Battery Charging Process
9.3.1.1.1
Pre-Charge
9.3.1.1.2
Fast Charge
9.3.1.1.3
Pre-Charge to Fast Charge Transitions and Charge Current Ramping
9.3.1.1.4
Termination
9.3.1.2
JEITA and Battery Temperature Dependent Charging
9.3.1.3
Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
9.3.1.4
Battery Supplement Mode
9.3.2
Protection Mechanisms
9.3.2.1
Input Over-Voltage Protection
9.3.2.2
Safety Timer and I2C Watchdog Timer
9.3.2.3
Thermal Protection and Thermal Charge Current Foldback
9.3.2.4
Battery Short and Over Current Protection
9.3.2.5
PMID Short Circuit
9.3.3
ADC
9.3.3.1
ADC Operation in Active Battery Mode and Low Power Mode
9.3.3.2
ADC Operation When VIN Present
9.3.3.3
ADC Measurements
9.3.3.4
ADC Programmable Comparators
9.3.4
VDD LDO
9.3.5
Load Switch/LDO Output and Control
9.3.6
PMID Power Control
9.3.7
System Voltage (PMID) Regulation
9.3.8
MR Wake and Reset Input
9.3.8.1
MR Wake or Short Button Press Functions
9.3.8.2
MR Reset or Long Button Press Functions
9.3.9
14-Second Watchdog for HW Reset
9.3.10
Faults Conditions and Interrupts ( INT)
9.3.10.1
Flags and Fault Condition Response
9.3.11
Power Good ( PG) Pin
9.3.12
External NTC Monitoring (TS)
9.3.12.1
TS Thresholds
9.3.13
External NTC Monitoring (ADCIN)
9.3.14
I2C Interface
9.3.14.1
F/S Mode Protocol
9.4
Device Functional Modes
9.4.1
Ship Mode
9.4.2
Low Power
9.4.3
Active Battery
9.4.4
Charger/Adapter Mode
9.4.5
Power-Up/Down Sequencing
9.5
Register Map
9.5.1
I2C Registers
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Input (IN/PMID) Capacitors
10.2.2.2
VDD, LDO Input and Output Capacitors
10.2.2.3
TS
10.2.2.4
Recommended Passive Components
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Third-Party Products Disclaimer
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Receiving Notification of Documentation Updates
13.4
Support Resources
13.5
Electrostatic Discharge Caution
13.6
Trademarks
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
12.2
Layout Example
Figure 12-1
Layout Example