SLUSDQ4 Data sheet

SLUSDQ4 April 2019 BQ79606A-Q1

PRODUCTION DATA.

8.5.1.8 Error Check and Correct (ECC) OTP

Register values for selected registers (0x0000 to 0x00C7) are permanently stored in OTP. All registers also exist as volatile storage locations at the same addresses, referred to as "shadow" registers. The volatile registers are for reading, writing, and device control. For a list of registers included in the OTP, see the Register Summary Table. During wakeup, the BQ79606A-Q1 first loads all shadow registers with hardware default values listed in the Register Summary. Then the BQ79606A-Q1 loads the registers conditionally with OTP contents from the results of the Error Check and Correct (ECC) evaluation of the OTP. The OTP is loaded to shadow registers in 64-bit blocks; each block has its own Error Check and Correct (ECC) value stored. The ECC detects a single-bit (Single-Error-Correction) or double-bit (Double-Error-Detection) changes in OTP stored data. The ECC is calculated for each block, individually. Single-bit errors are corrected, double-bit errors are only detected, not corrected. A block with good ECC is loaded. A block with a single-bit error is corrected, and the SYS_FAULT3[SEC_DET] bit is set to flag the corrected error event. Additionally, the SEC_BLK register is updated with the location of the error corrected block. This enables the host to keep track of potentially damaged memory. The block is loaded to shadow registers after the single-bit error correction. Since the evaluation is on a block-by-block basis, it is possible for multiple blocks to have a single-correctable error and still be loaded correctly. Multiple-bit errors can exist with full correction, as long as they are limited to a single error per block. A block with a bad ECC comparison (two-bit errors in one block) is not loaded and the SYS_FAULT3[DED_DET] bit is set to flag the failed bit-error event. Additionally, the DED_BLK register is updated with the block where the double error occurred. The hardware default value remains in the register. This allows some blocks to be loaded correctly (no fail or single-bit corrected value) and some blocks not to load. When either of the SYS_FAULT3[SEC_DET] or SYS_FAULT3[DED_DET] is set, and the condition is not cleared by a device reset (write CONTROL1[SOFT_RESET] or a WAKE command), the device is corrupted and must not be used.

The ECC engine uses the industry standard 72,64 SEC DEC ECC implementation. The OTP is protected by a (72, 64) Hamming code, providing single error correction, double error detection (SECDED). For each 64-bits of data stored in OTP, an additional 8-bits of parity information are stored. Therefore, the ECC code imposes an area overhead on the OTP of (72 – 64) / 64, or 12.5%. The parity bits are designated p0, p1, p2, p4, p8, p16, p32 and p64. Bit p0 covers the entire encoded 72- bit ECC block. The remaining seven parity bits are assigned according to the following rule:

1. Parity bit p1 covers odd bit positions, i.e. bit positions which have the least significant bit of the bit position equal to 1 (1, 3, 5, etc.), including the p1 bit itself (bit 1).

2. Parity bit p2 covers bit positions which have the second least significant bit of the bit position equal to 1 (2, 3, 6, 7, 10, 11, etc.), including the p2 bit itself (bit 2).

The pattern continues for p4, p8, p16, p32 and p64. Table below specifies the complete encoding.

Table 26. (72, 64) Parity Encoding

Bit Position		71	70	69	68	67	66	65	64	63	62	61	60	59	58	57	56	55	54
Encoded Bits		d63	d62	d61	d60	d59	d58	d57	p64	d56	d55	d54	d53	d52	d51	d50	d49	d48	d47
Parity Bit Coverage	p0	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x
	p1	x		x		x		x		x		x		x		x		x
	p2	x	x			x	x			x	x			x	x			x	x
	p4	x	x	x	x					x	x	x	x					x	x
	p8									x	x	x	x	x	x	x	x
	p16									x	x	x	x	x	x	x	x	x	x
	p32									x	x	x	x	x	x	x	x	x	x
	p64	x	x	x	x	x	x	x	x
Bit Position		53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36
Encoded Bits		d46	d45	d44	d43	d42	d41	d40	d39	d38	d37	d36	d35	d34	d33	d32	d31	d30	d29
Parity Bit Coverage	p0	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x
	p1	x		x		x		x		x		x		x		x		x
	p2			x	x			x	x			x	x			x	x
	p4	x	x					x	x	x	x					x	x	x	x
	p8							x	x	x	x	x	x	x	x
	p16	x	x	x	x	x	x
	p32	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x
	p64
Bit Position		35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18
Encoded Bits		d28	d27	d26	p32	d25	d24	d23	d22	d21	d20	d19	d18	d17	d16	d15	d14	d13	d12
Parity Bit Coverage	p0	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x
	p1	x		x		x		x		x		x		x		x		x
	p2	x	x			x	x			x	x			x	x			x	x
	p4					x	x	x	x					x	x	x	x
	p8					x	x	x	x	x	x	x	x
	p16					x	x	x	x	x	x	x	x	x	x	x	x	x	x
	p32	x	x	x	x
	p64
Bit Position		17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Encoded Bits		d11	p16	d10	d9	d8	d7	d6	d5	d4	p8	d3	d2	d1	p4	d0	p2	p1	p0
Parity Bit Coverage	p0	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x
	p1	x		x		x		x		x		x		x		x		x
	p2			x	x			x	x			x	x			x	x
	p4			x	x	x	x					x	x	x	x
	p8			x	x	x	x	x	x	x	x
	p16	x	x
	p32
	p64

Table 27. Encoder and Decoder Data IN and OUT Positioning

ENCODER
DATA IN	Encoded Bits	DATA OUT	Bit Position
ECC_DATAIN 0	d0 to d7	ECC_DATAOUT0	0 to 7
ECC_DATAIN 1	d8 to d15	ECC_DATAOUT1	8 to 15
ECC_DATAIN 2	d16 to d23	ECC_DATAOUT2	16 to 23
ECC_DATAIN 3	d24 to d31	ECC_DATAOUT3	24 to 31
ECC_DATAIN 4	d32 to d39	ECC_DATAOUT4	32 to 39
ECC_DATAIN 5	d40 to d47	ECC_DATAOUT5	40 to 47
ECC_DATAIN 6	d48 to d55	ECC_DATAOUT6	48 to 55
ECC_DATAIN 7	d56 to d63	ECC_DATAOUT7	56 to 63
		ECC_DATAOUT8	64 to 71
DECODER
DATA IN	Bit Position	DATA OUT	Decoded Bits
ECC_DATAIN 0	0 to 7	ECC_DATAOUT0	d0 to d7
ECC_DATAIN 1	8 to 15	ECC_DATAOUT1	d8 to d15
ECC_DATAIN 2	16 to 23	ECC_DATAOUT2	d16 to d23
ECC_DATAIN 3	24 to 31	ECC_DATAOUT3	d24 to d31
ECC_DATAIN 4	32 to 39	ECC_DATAOUT4	d32 to d39
ECC_DATAIN 5	40 to 47	ECC_DATAOUT5	d40 to d47
ECC_DATAIN 6	48 to 55	ECC_DATAOUT6	d48 to d55
ECC_DATAIN 7	56 to 63	ECC_DATAOUT7	d56 to d63
ECC_DATAIN 8	64 to 71