SLUSDQ4 April 2019 BQ79606A-Q1
PRODUCTION DATA.
OTUT_BIST_FLT_MSK Register Address: 0x1A | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
MUX6_MSK | MUX5_MSK | MUX4_MSK | MUX3_MSK | MUX2_MSK | MUX1_MSK | UTCOMP_MSK | OTCOMP_MSK |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RW | RW | RW | RW | RW | RW | RW | RW |
MUX6_MSK | Enables mask for OTUT_BIST_FAULT[MUX6]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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MUX5_MSK | Enables mask for OTUT_BIST_FAULT[MUX5]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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MUX4_MSK | Enables mask for OTUT_BIST_FAULT[MUX4]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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MUX3_MSK | Enables mask for OTUT_BIST_FAULT[MUX3]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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MUX2_MSK | Enables mask for OTUT_BIST_FAULT[MUX2]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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MUX1_MSK | Enables mask for OTUT_BIST_FAULT[MUX1]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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UTCOMP_MSK | Enables mask for OTUT_BIST_FAULT[UTCOMP]
0: Mask disabled 1: Mask enabled to prevent fault signaling |
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OTCOMP_MSK | Enables mask for OTUT_BIST_FAULT[OTCOMP]
0: Mask disabled 1: Mask enabled to prevent fault signaling |