SLUSDQ4 Data sheet

SLUSDQ4 April 2019 BQ79606A-Q1

PRODUCTION DATA.

7.6 Timing Requirements

V_BAT = 5.5V to 30V, all LDOs operating in regulation, Typical Applications Circuit used, 3 to 6 cells connected, –40°C to +105°C free-air temperature range (unless otherwise noted)

PARAMETERS		TEST CONDITIONS	MIN	NOM	MAX	UNIT
State Change Timing
t_SU(WAKE)	SHUTDOWN to ACTIVE transition time with WAKEUP command	V_BAT > 4.75V (CLDO=2.2uF) and in SHUTDOWN mode, WAKEUP command or WAKE tone received. For base: From the WAKEUP goes High to the first couplet of wakeup tone send out. For Stack: From last couplet of wakeup tone recieved to the first couplet of wakeup tone send out.			7	ms
t_{SU(SLPtoACT)1}	SLEEP to ACTIVE transition time with SLEEPtoACTIVE command	V_BAT > 4.75V, (CLDO=2.2uF). For base: From the RX pin goes high to the first couplet of Sleep to Active tone send out. For Stack: From last couplet of Sleep to Active tone received to the first couplet of sleep to active tone send out.			170	µs
t_{SU(SLPtoACT)2}	SLEEP to ACTIVE transition time with WAKEUP command	V_BAT > 4.75V, (CLDO=2.2uF). For base: From the WAKEUP pin goes high to the first couplet of wake up tone send out. For Stack: From last couplet of wake up tone received to the first couplet of wake up tone send out.			500	µs
t_SDorSLP	Transition time to SLEEP or SHUTDOWN	V_BAT > 4.75V, communication timeout short, SLEEP command received, Communication timeout long, SHUTDOWN command, shutdown pulse, or shutdown tone received (from the shutdown or sleep command recieved to 90% of REF1).			105	µs
t_PORtoWKRDY	Transition to SHUTDOWN from POR (initial power up time)	VBAT<POR to VBAT>POR, time to be ready for WAKE command- See start up diagram (BAT POR (4.75V) to VLDO>CVDDUV)		4		ms
t_RESET	Reset time during ACTIVE mode	WAKE tone, WAKEUP, or SOFT_RESET command received while in ACTIVE state. From the end of the tone or command or pulse to the time the first couplet send out.		500		µs
t_WKDLY(BS)	Delay after state transition to send WAKE or SLEEPtoACTIVE tone for Base device or Bridge	V_BAT > 4.75V, time to start of first tone pulse, with max capacitance and min LDO current limit		3.3		ms
t_WKDLY(SK)	Delay after state transition to send WAKE or SLEEPtoACTIVE tone for stack device	V_BAT > 4.75V, time to start of first tone pulse, with max capacitance and min LDO current limit		3.3		ms
f_REF1OSC	Detectable REF1 oscillation frequency	Amplitude > V_REF1SWING	0.2		10	MHz
t_REF1OSCFLT	Delay time from REF1 oscillation to fault indication			1.5		µs
ADC Timings
f_ALIAS	Internal anti-alias filter corner frequency for CELL ADCs and AUX ADC (when doing AUX_CELL_SEL measurement)	–3 dB		1.5		kHz
t_DLY(COM)	Internal filter settling time after enabling the level shifters	Host must wait for this time after device enables the CELL level shifters before requesting an ADC conversion			5	ms
t_CONV32	ADC conversion time (CELL and AUX)	DR=32, time from ADCGO to data available	211	214	218	µs
t_CONV64	ADC conversion time (CELL and AUX)	DR=64, time from ADCGO to data available	306	311	316	µs
t_CONV128	ADC conversion time (CELL and AUX)	DR=128, time from ADCGO to data available	495	503	511	µs
t_CONV256	ADC conversion time (CELL and AUX)	DR=256, time from ADCGO to data available	873	887	901	µs
t_DELAY	Programmable delay from conversion command to start of conversion	Programmable range ADC_DELAY[DLY]. Total delay is t_{DLY_CELL} + t_DELAY or t_{DLY_AUX} + t_DELAY	0		155	us
t_AUXDLY	Delay between measurements for auxiliary ADC	Allows for settling of the MUX when cycling through inputs			10.5	µs
Cell Balancing
t_BAL	Balance timer accuracy		-10%		11.5%
t_DEAD	Delay from switching from ODD to EVEN or EVEN to ODD			5		µs
t_CYCLE	Total CBDONE, OV/UV, and OT/UT round-robin monitoring cycle time	Cell balancing, OV/UV, or OT/UT enabled		17		ms
t_{RR_SLOT}	Indiviual cell or GPIO monitoring time during the round-robin cycle	Cell balancing, OV/UV or OT/UT enabled		2		ms
t_dgOVUVCB	CBDONE, Over-voltage and under-voltage comparator programmable deglitch range.	Programmable in COMP_DG[OVUV_DG]	25		500	µs
t_dgACC	Accuracy on hardware comparator deglitch times		–10%		11.5%
Oscillator
f_HFO	High frequency oscillator frequency	V_BAT > 4.5V	31.52	32	32.48	MHz
t_HFOWD	High frequency oscilator (HFO) watchdog time	VBAT > 4.75V, sends device to RESET if oscillator stuck high or low for longer than this time	5		40	µs
f_LFO	Low frequency oscillator frequency		235.8	262	288.2	kHz
f_LFOWD	Low frequency oscillator (LFO) watchdog time	V_BAT > 4.75V, flags error if oscillator is stuck high or low for longer than this time		35		µs
Digital I/Os (TX, RX, GPIO_, NFAULT, WAKEUP)
t_OUTRISE	Rise time (TX, GPIO*)	V_VIO=4.8V, C_LOAD=150pF, GPIO in output mode		12		ns
t_OUTFALL	Fall time (TX, GPIO*)	V_VIO=4.8V, C_LOAD=150pF, GPIO in output mode		12		ns
t_FALLNFLT	Fall time (NFAULT)	V_VIO=4.8V, R_PULLUP = 10kΩ, C_LOAD=150pF		35		ns
t_{dg_GPIO}	Deglitch for GPIO for fault indication	fault enabled		45		µs
t_{HLD_WAKE}	WAKEUP input hold time for WAKE command (low-pulse width) (max value guaranties a wake up of the device and below min should guarantiy no wake up)	V_BAT ≥ 4.75V	250		300	µs
t_{HLD_SD}	WAKEUP input hold time for SHUTDOWN command (low-pulse width) (max value guaranties a shutdown of the device and below the min should guaranties no shutdown)	V_BAT ≥ 4.75V	1400		1600	µs
SPI Master Interface
f_SCLK	SCLK frequency		450	500	550	kHz
t_HIGH:tLOW	SCLK duty cycle		40	50	60	%
t_SS,HI	SS hi latency time. Time from register write high to SS high			1		µs
t_SS,LOW	SS low latency time. Time from register write low to SS low			1		µs
t_SU,MISO	MISO input data setup time	MISO stable before SCLK transition	100			ns
t_HD,MISO	MISO input data hold time	MISO stable after SCLK transition		0		ns
t_{VALID, MOSI}	MOSI output data valid time	MOSI stable after SCLK transition		10	20	ns
t_MOSI,DIS	SS disable time to MOSI high impedance (tri-state)			20	50	ns
t_{dg_GPIO}	Deglitch for GPIO for fault indication	GPIO*_CONF[FAULT_EN]≠0b00		25		µs
Daisy-Chain Communication Interface
t_{PW_DC}	Pulse width of data (half bit time) for communication	V_BAT > 4.75V	230	250	270	ns
t_{RECLK_DC}	Data re-clocking delay per device (COMH to COML or vice versa depending on communication direction)	V_BAT > 4.75V, ACTIVE mode		3		µs
n_WAKEDET	WAKE tone receive threshold	V_BAT > 4.75V		20		pulses
n_WAKE	WAKE tone sending duration	V_BAT > 4.75V		40		pulses
n_SLPtoACTDET	SLEEPtoACTIVE tone receive threshold	V_BAT > 4.75V		20		pulses
n_SLPtoACT	SLEEPtoACTIVE tone sending duration	V_BAT > 4.75V		40		pulses
n_SHDNDET	SHUTDOWN tone receive threshold	V_BAT > 4.75V		100		pulses
n_SHDN	SHUTDOWN tone sending duration	V_BAT > 4.75V		185		pulses
n_FLTTONEDET	Fault tone detection threshold	V_BAT > 4.75V, fault condition present		20		pulses
n_FLTONE	Fault tone sending duration	V_BAT > 4.75V, fault condition present		40		pulses
t_FLTRETRY	Fault tone retry during persistent fault condition	V_BAT > 4.75V, fault condition present		50		ms
n_FLTHBDET	Heartbeat tone detection threshold	V_BAT > 4.75V, no fault present, heartbeat enabled		20		pulses
n_HBTONE	Heartbeat tone sending duration	V_BAT > 4.75V, no fault present, heartbeat enabled		40		pulses
t_WAITHB	Time between heartbeat tones	V_BAT > 4.75V, no fault present, heartbeat enabled		400		ms
t_HBTO	Heartbeat fault timeout	V_BAT > 4.75V, fault signaled if no heartbeat received with t_HBTO		1		s
t_HBFAST	Heartbeat received to fast threshold	V_BAT > 4.75V, fault signaled if the time between heartbeat tones is less than t_HBFAST		200		ms
t_{FLTTONE_HI}	Fault pulse high time (analog delay based)			1		µs
t_{FLTTONE_LO}	Fault pulse low time			1		µs
t_FLTTONE	Time between pulses within a fault tone (LFO based). From the begning of a pulse untill the begining of the next pulse.			11.5		µs
t_COMTONE	Time between pulses within a comms tone (HFO based). From the begning of a pulse untill the begining of the next pulse.			11		µs
t_{TONE_HI}	Comms pulse high time (HFO based)			1		µs
t_{TONE_LO}	Comms pulse low time (HFO based)			1		µs
t_{FTS_Latency}	Fault Tone Latency in stack device	Latency from fault tone received/detected to fault tone going out in a stack device.		48		µs
t_{FTB_Latency}	Fault Tone Latency in base device	Latency from fault tone received/detected in base device to NFAULT tone going out.		24		µs
UART Interface
RXTX_BAUD	RX/TX signaling rate adjustable range	V_BAT > 4.75V	125		1000	kbps
ERR_BD(RX)	Input baud rate error	V_BAT > 4.75V	–1.5%		1.5%
ERR_BD(TX)	Output baud rate error	V_BAT > 4.75V	–1.5%		1.5%
t_UART(BRK)	Communications clear (break) time	V_BAT > 4.75V	15		20	bit periods
t_UART(StA)	SLEEPtoACTIVE time	V_BAT > 4.75V, RX held low	250		300	µs
t_UART(RST)	Communications reset time	V_BAT > 4.75V, RX held low	450			µs
t_UART(RXMIN)	Minimum RX high time after Communications Clear received		1			bit periods
Safety Diagnostics
t_VIOUVDGL	Under-voltage deglitch on VIO	V_VIO rising. V_VIO< V_VIOUV threshold to corresponding flag set		25		µs
t_OVDGL	Over-voltage deglitch on supply rails (AVDD, DVDD)	V_SUPPLY rising. V_SUPPLY> VOV threshold to corresponding flag set		25		µs
t_OVCVDDDGL	Over-voltage deglitch on VLDO supply rail	V_VLDO rising. V_VLDO> VOV threshold to corresponding flag set		250		µs
t_UVDGL	Under-voltage deglitch on supply rails (AVDD, CVDD)	V_SUPPLY falling. V_SUPPLY < VUV threshold to corresponding flag set		25		µs
t_DVDDPORDGL	POR deglitch for DVDD supply	V_DVDD falling. V_DVDD < V_DVDDPOR threshold to device power down		25		µs
t_TSREFBLNK	TSREF startup blanking time (TSREF OV/UV and the OTUT function ignored)	TSREF startup		2		ms
t_TSREFDG	TSREF OV/UV deglitch time setting	After t_TSREFBLK expires, V_TSREF rising orfalling.		25		µs
t_BISTDG	Deglitch for BIST for hardware comparators	BIST enabled for OVUV and/or OTUT		25		µs
t_AVDDREFUVDGL	Deglitch on internal AVDD_REF under-voltage			25		µs
t_AVAODGL	Deglitch on internal AVAO_REF protections (OV, UV, SW)			25		µs
t_CBVCDGL	Deglitch on CBVC comparators			25		µs
t_VCLOWDGL	Deglitch on VCLOW comparators			25		µs
t_TSHUTDGL	Thermal shutdown comparator deglitch	Temperature rising. T_J > T_SHUT to device shut down		25		µs
t_{VSS_OPEN}	Open VSS fault deglitch time (CVSS_OPEN, DVSS_OPEN)			25		µs
t_{RAIL_OSC}	Rail oscillation fault deglitch time (AVDD_OSC, TSREF_OSC, REF1_OSC)			25		µs
f_{LFO_CHECK}	LFO frequency checker	Sets SYS_FAULT3[LFO_FLT] when LFO frequency is outside of this range	196.5		327.5	kHz
t_{CRC_COM}	Communication CRC validation time	V_BAT > 4.75V			2	µs
t_{CRC_OTP}	Period for auto CRC updates on NVM	V_BAT > 4.75V			2	ms
t_{OVUV_BIST}	BIST time for OVUV and CBDONE round-robin	BIST enabled, uses LFO, measured from reset expired		4.5		ms
t_{OTUT_BIST}	BIST time for OTUT round-robin	BIST enabled, uses LFO, measured from reset expired		2.4		ms
t_BISTDG	Deglitch on checks during OVUV, CBDONE, and OTUT BIST	BIST enabled		25		µs