SLUSES3B October   2023  – July 2024 UCC25660

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brown in and Brown out Tresholds and Options
        2. 7.3.5.2 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Startup
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Threshold Programming
        4. 7.5.3.4 PFC On/Off
      4. 7.5.4 X-Capacitor Discharge
        1. 7.5.4.1 Detecting Through HV Pin Only
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
        2. 8.4.2.2 Schematics
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Burst Mode Programming

The LL pin voltage (VLLB) and the resistor divider that connected to the LL pin allow the designer to set the HFBurstEntry and LFBurstEntry thresholds as shown below.

Equation 73. V L L B = R L L _ l o w e r V 5 P R L L _ u p p e r + R L L _ l o w e r
Equation 74. V L L A = V L L B + R L L _ l o w e r R L L _ u p p e r R L L _ u p p e r + R L L _ l o w e r I L L P r g m

As shown in Table 7-2, (VLLA-VLLB) voltage determines the VLLB/HFBurstEntry ratio.

For this design, (VLLB/HFBurstEntry) = 0.55 is considered. So, Max voltage of (VLLA-VLLB) should be below 1.391V.

Then HFBurstEntry is related to LL pin voltage as below:

Equation 75. H F B u r s t E n t r y = V L L B 0.55 = 1.818 V L L B

The LFBurstEntry is always related to LL pin voltage as below:

Equation 76. L F B u r s t E n t r y = V L L B 0.6 = 1.667 V L L B

For this design, VLLB= 1V and VLLA=(Max voltage of (VLLA-VLLB))-0.1V are considered. By substituting these values in Equation 73, Equation 74, RLLupper, RLLlower can be obtained as 641k and 161k respectively.

Finally RLLupper= 549kΩ and RLLlower=140kΩ are chosen for this design.

Then final burst entries will be calculated as below.

Equation 77. V L L B = 140 k 5 140 k + 549 k = 1.016 V
Equation 78. VLLA=1.016V+ 140k549k 140k+549k 10μA=2.131V
Equation 79. VLLAVLLB=1.116V
Equation 80. HFBurstEntry=1.8181.016=1.847V
Equation 81. LFBurstEntry=1.6671.016=1.693V