SLUSEU6D May   2023  – August 2024 UCC21550-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Disable Response Time
    4. 6.4 Programmable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21550-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead-Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information
    2. 13.2 Mechanical Data

12 Revision History

Changes from Revision C (June 2024) to Revision D (August 2024)

  • Added tape and reel informationGo
  • Added mechanical dataGo

Changes from Revision B (November 2023) to Revision C (June 2024)

  • Removed HBD ESD and CDM ESD classification levels per datasheet standard changeGo
  • Added new device spinsGo
  • Changed typical application schematic disable capacitor namingGo
  • Added DWK package drawingGo
  • Added recommendation on DT capacitor sizeGo
  • Added ch-ch isolation voltage for DWK packageGo
  • Changed HBM ESD from +/-4000V to +/-2000VGo
  • Added 12V UVLO spinGo
  • Added thermal information for DWK packageGo
  • Updated overvoltage category of ≤600Vrms from I-IV to I-III per latest standardGo
  • Updated overvoltage category of ≤1000Vrms from I-III to I-II per latest standardGo
  • Updated VDE to latest standardGo
  • Added safety limiting values for DWK packageGo
  • Changed test condition from EN=VCC to DIS=GNDGo
  • Changed VCC quiescent current typical and max to tighten specGo
  • Changed VDD quiescent current typical and maxGo
  • Added 12V UVLO spinGo
  • Added minimum propagation delay of 26nsGo
  • Changed typical DIS delay from 49ns to 48nsGo
  • Changed typical minimum input pulse from 9ns to 12nsGo
  • Changed TDDB curve to match basic isolationGo
  • Added thermal derating limiting current and limiting power curves for DWK packageGo
  • Added typical characteristics plot for 12V UVLOGo
  • Changed plot titles to reflect DIS spinsGo
  • Changed typical application schematic disable capacitor namingGo

Changes from Revision A (October 2023) to Revision B (November 2023)

  • Changed UCC21550AQDWRQ1 from Advance Information to Production DataGo
  • Changed data sheet status from Production Data Mixed Status to Production Data StatusGo

Changes from Revision * (May 2023) to Revision A (October 2023)

  • Changed UCC21550BQDWRQ1 from Product Preview to Production DataGo
  • Changed data sheet status from Advance Information Mixed Status to Production Data Mixed StatusGo