SLUSF08A March   2024  – September 2024 TPS1213-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving
        1. 7.3.2.1 Using Low Power Bypass FET (G2 drive) for Load Capacitor Charging
        2. 7.3.2.2 Using Main FET (G1 Drive) Gate Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 State Transition Timing Diagram
      3. 7.4.3 Power Down
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 Low Power Mode
      6. 7.4.6 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application 1: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application 2: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 8.3.1 Design Requirements
      2. 8.3.2 External Component Selection
      3. 8.3.3 Application Curves
    4. 8.4 TIDA-020065: Automotive Smart Fuse Reference Design Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup, Output Bulk Capacitor Charging, Bi-directional Current Sensing and Software I2t
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

7.3.3 Short-Circuit Protection

The TPS12130-Q1 feature adjustable short circuit protection. The threshold and response time can be adjusted using RISCP resistor and CTMR capacitor respectively. The device senses the voltage across CS+ and CS– pins. These pins can be connected across the FET drain and source terminals for FET RDSON sensing or across an external current sense resistor (RSNS) as shown in Figure 7-7 and Figure 7-8 respectively.

TPS1213-Q1 TPS12130-Q1 Application Circuit With Main FET RDSON Based Current SensingFigure 7-7 TPS12130-Q1 Application Circuit With Main FET RDSON Based Current Sensing
TPS1213-Q1 TPS12130-Q1 Application Circuit With External Sense Resistor RSNS Based Current SensingFigure 7-8 TPS12130-Q1 Application Circuit With External Sense Resistor RSNS Based Current Sensing

Set the hard short-circuit detection threshold using an external RISCP resistor across ISCP/LWU and GND pins. Use Equation 8 to calculate the required RISCP value:

Equation 8. R I S C P   ( Ω )   =   I S C   ×   R S N S   -   19   m V 2   µ A

Where,

RSNS is the current sense resistor value or the FET RDSON value.

ISC is the desired short circuit current level.

The hard short circuit protection response is fastest < 10μs with no CTMR cap connected across TMR and GND pins.

With device powered ON and EN/UVLO, INP pulled high, during Q1 turn ON, first VGS of main FET is sensed by monitoring the voltage across G1PD to SRC. Once G1PD to SRC voltage raises above V(G1_GOOD) threshold which ensures that the external FET is enhanced, then the SCP comparator output is monitored. If the sensed voltage across CS+ and CS– exceeds the short-circuit set point (VSCP/LWU), G1PD pulls low to SRC and FLT asserts low within 10μs (with TMR pin open). Subsequent events can be set either to be auto-retry or latch off as described in following sections.