SLUSF08 March 2024 TPS1213-Q1
ADVANCE INFORMATION
Figure 7-1 shows a simplified diagram of the charge pump and gate driver circuit implementation. The device houses a strong 1.69-A/2-A peak source/sink gate driver (G1) for main FET and 165-µA/2-A peak source/sink current gate driver (G2) for bypass FET. The strong gate drivers enable paralleling of FETs in high power system designs ensuring minimum transition time in saturation region. A 11-V, 345-µA charge pump is derived from VS terminal and charges the external boot-strap capacitor, CBST that is placed across the gate driver (BST and SRC).
VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and charges the CBST capacitor. After the voltage across CBST crosses V(BST_UVLOR), the GATE driver section is activated. The device has a 1-V (typical) UVLO hysteresis to ensure chattering less performance during initial GATE turn ON. Choose CBST based on the external FET QG and allowed dip during FET turn-ON. The charge pump remains enabled until the BST to SRC voltage reaches 11.8 V, typically, at which point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to SRC voltage discharges to 10 V typically at which point the charge pump is enabled. The voltage between BST and SRC continue to charge and discharge between 11.8 V and 10 V as shown in the Figure 7-2.
Use the following equation to calculate the initial gate driver enable delay:
Where,
CBST is the charge pump capacitance connected across BST and SRC pins.
V(BST_UVLOR) = 9.5 V (max).