SLUSF08A March 2024 – September 2024 TPS1213-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE | ||||||
VS | Operating input voltage | 3.5 | 40 | V | ||
I(Q) | Total System Quiescent current, I(GND) in Active mode | V(EN/UVLO) = V(LPM) = 2 V | 43 | 55 | µA | |
Total System Quiescent current, I(GND) in low power mode | V(EN/UVLO) = 2 V, V(LPM) = 0 V | 35 | 44 | µA | ||
V(EN/UVLO) = 2 V, V(LPM) = 0 V, –40°C ≤ TJ ≤ +85°C | 43 | µA | ||||
I(SHDN) | SHDN current, I(GND) | V(EN/UVLO) = 0 V, V(SRC) = 0 V | 1 | 3.3 | µA | |
I(REV) | I(VS) leakage current during Reverse Polarity | V(VS) = – 40 V | 11 | 13 | 23 | µA |
ENABLE, UNDERVOLTAGE LOCKOUT (EN/UVLO), SHORT CIRCUIT COMPARATOR TEST (SCP_TEST) INPUT | ||||||
V(UVLOR) | UVLO threshold voltage, rising | 1.179 | 1.23 | 1.28 | V | |
V(UVLOF) | UVLO threshold voltage, falling | 1.06 | 1.13 | 1.178 | V | |
V(ENR) | Enable threshold voltage for low Iq shutdown, rising | 1 | V | |||
V(ENF) | Enable threshold voltage for low Iq shutdown, falling | 0.3 | V | |||
I(EN/UVLO) | Enable input leakage current | V(EN/UVLO) = 12 V | 180 | 305 | nA | |
V(SCP_TEST_H) | SCP test mode rising threshold | 2 | V | |||
V(SCP_TEST_L) | SCP test mode falling threshold | 0.8 | V | |||
I(SCP_TEST) | SCP_TEST input leakage current | 90 | 700 | nA | ||
CHARGE PUMP (BST–SRC) | ||||||
I(BST) | Charge Pump Supply current | V(BST – SRC) = 10 V, V(EN/UVLO) = 2 V | 200 | 345 | 466 | µA |
V(BST_UVLOR) | V(BST – SRC) UVLO voltage threshold, rising | V(EN/UVLO) = 2 V | 8.1 | 9 | 9.9 | V |
V(BST_UVLOF) | V(BST – SRC) UVLO voltage threshold, falling | V(EN/UVLO) = 2 V | 7.31 | 8.2 | 8.9 | V |
V(BST–SRC_ON) | Charge Pump Turn ON voltage | V(EN/UVLO) = 2 V | 9.3 | 10.3 | 11.4 | V |
V(BST–SRC_OFF) | Charge Pump Turn OFF voltage | V(EN/UVLO) = 2 V | 10.4 | 11.6 | 12.8 | V |
V(BST–SRC) | Charge Pump Voltage at V(VS) = 3.5 V | V(EN/UVLO) = 2 V | 9.1 | 10.5 | 11.6 | V |
V(G1_GOOD) | G1 Good rising threshold | 5.5 | 7 | 8.3 | V | |
V(G2_GOOD) | G2 Good rising threshold | 5.5 | 7 | 8.3 | V | |
GATE DRIVER OUTPUTS (G1PU, G1PD, G2) | ||||||
I(G2) | G2 Source Current | 134 | 165 | 189 | µA | |
I(G2) | G2 Peak Sink Current | 2 | A | |||
I(G1PU) | Peak Source Current | 1.69 | A | |||
I(G1PD) | Peak Sink Current | 2 | A | |||
SHORT CIRCUIT PROTECTION AND LOAD WAKE UP THRESHOLD (ISCP/LWU) | ||||||
ISCP/LWU | SCP/LWU Input Bias current | 8.4 | 10 | 12.33 | µA | |
V(SCP/LWU) | SCP/LWU threshold | R(ISCP/LWU) = 140.5 kΩ | 300 | mV | ||
R(ISCP/LWU) = 28 kΩ | 60 | 75 | 90 | mV | ||
R(ISCP/LWU) = 10.5 kΩ | 32 | 40 | 48 | mV | ||
R(ISCP/LWU) = 500 Ω | 15 | 20 | 25 | mV | ||
R(ISCP/LWU) = Open | 757 | mV | ||||
DELAY TIMER (TMR) | ||||||
I(TMR_SRC_CB) | TMR source current | 67 | 87 | 104 | µA | |
I(TMR_SRC_FLT) | TMR source current | 1.4 | 2.73 | 3.8 | µA | |
I(TMR_SNK) | TMR sink current | 2.17 | 2.8 | 3.4 | µA | |
V(TMR_SC) | 0.93 | 1.1 | 1.2 | V | ||
V(TMR_LOW) | 0.15 | 0.21 | 0.25 | V | ||
N(A-R Count) | 32 | |||||
INPUT CONTROLS (INP, LPM), FAULT (FLT) & WAKE FLAG (WAKE) | ||||||
R(FLT), R(WAKE) | FLT, WAKE Pull-down resistance | 53 | 70 | 105 | Ω | |
I(FLT), I(WAKE) | FLT, WAKE Input leakage current | 0 V ≤ V(FLT) ≤ 20 V | 410 | nA | ||
V(INP_H), V(LPM_H) | 2 | V | ||||
V(INP_L), V(LPM_L) | 0.8 | V | ||||
I(INP), I(LPM) | INP, LPM Input leakage current | 69 | 89 | 206 | nA |