Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the components minimizing high-frequency current path loop is important to prevent electrical and magnetic field radiation and high-frequency resonant problems. This PCB layout priority list must be followed in the order presented for proper layout:
- Place the input capacitor as close as
possible to the PMID pin and GND pin connections and use the shortest copper trace
connection or GND plane.
- Place the inductor input terminal as close
to the SW pin as possible. Minimize the copper area of this trace to lower electrical and
magnetic field radiation but make the trace wide enough to carry the charging current. Do
not use multiple layers in parallel for this connection. Minimize parasitic capacitance
from this area to any other trace or plane.
- Put an output capacitor near to the inductor and the IC. Tie ground
connections to the IC ground with a short copper trace connection or GND plane.
- Place decoupling capacitors next to the IC pins and make the trace
connection as short as possible.
- It is critical that the exposed power pad on the backside of the IC
package be soldered to the PCB ground. Ensure that there are sufficient thermal vias
directly under the IC connecting to the ground plane on the other layers.
- The via size and number should be enough for a given current path.
- For more layout guidelines and
recommendations refer to the data sheet of the respective battery charger IC.
- See the EVM design for the recommended
component placement with trace and via locations. For the QFN information, refer to Quad Flatpack
No-Lead Logic Packages Application Report and QFN and SON PCB Attachment
Application Report.