SLUUCJ3A February   2022  – March 2022 TPS565242 , TPS565247

 

  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
    1. 3.1 Output Voltage Setpoint
  5. 4Test Setup and Results
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Efficiency
    4. 4.4 Load Regulation
    5. 4.5 Line Regulation
    6. 4.6 Load Transient Response
    7. 4.7 Output Voltage Ripple
    8. 4.8 Start-Up
    9. 4.9 Shutdown
  6. 5Board Layout
    1. 5.1 Layout
  7. 6Schematic and List of Materials
    1. 6.1 Schematic
    2. 6.2 List of Materials
  8. 7Reference
  9. 8Revision History

5.1 Layout

Figure 5-1, Figure 5-2, and Figure 5-3 shows the board layout for the TPS565242EVM. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS565242 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors C3 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the signal ground copper fill and the feedback trace from the point of regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2-oz copper thickness.

Figure 5-4 and Figure 5-5 are the TPS565242EVM board top view and bottom view, respectively.

Figure 5-1 TPS565242EVM Top Assembly
Figure 5-2 TPS565242EVM Top Layer
Figure 5-3 TPS565242EVM Bottom Layer
Figure 5-4 TPS565242EVM Board (Top View)
Figure 5-5 TPS565242EVM Board (Bottom View)