SLUUCV7 December   2023 TPS1213-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 General Configurations
      1. 2.1.1 Physical Access
      2. 2.1.2 Test Equipment and Setup
        1. 2.1.2.1 Power Supplies
        2. 2.1.2.2 Meters
        3. 2.1.2.3 Oscilloscope
        4. 2.1.2.4 Loads
  8. 3Implementation Results
    1. 3.1 Test Setup and Procedures
      1. 3.1.1 Startup in Low Power Mode
      2. 3.1.2 State Transition (LPM to Active Mode through Load Wakeup Trigger)
      3. 3.1.3 State Transition (LPM to Active Mode with LPMb Trigger)
      4. 3.1.4 Inrush Current Limit Test
      5. 3.1.5 Overload and Short Circuit Protection Test
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill Of Materials (BoM)
  10. 5Additional Information
    1.     Trademarks

PCB Layout

Figure 5-15 and Figure 5-3 shows component placement of the EVAL Board, and Figure 5-4 through Figure 5-7 show PCB layout images.

GUID-20231128-SS0I-HJXX-HXC7-BQ495GVGCTBM-low.svgFigure 4-2 TPS1213Q1EVM Board Top Overlay
GUID-20231128-SS0I-5BTQ-HW2L-0NNF3D6Z4V3H-low.svgFigure 4-4 TPS1213Q1EVM Board Top Layer
GUID-20231128-SS0I-J5RG-K034-XDH0BWQ6LCWD-low.svgFigure 4-6 TPS1213Q1EVM Board Inner Signal Layer
GUID-20231128-SS0I-HPSM-LGNM-RCBVQV1SFXZ9-low.svgFigure 4-3 TPS1213Q1EVM Board Bottom Overlay
GUID-20231128-SS0I-CH82-NRMF-KQH85P8QNLHZ-low.svgFigure 4-5 TPS1213Q1EVM Board Bottom Layer
GUID-20231128-SS0I-CZX2-C0KB-3BVWT6LTWJ3W-low.svgFigure 4-7 TPS1213Q1EVM Board Inner Routing Layer