SLUUCZ0 April   2024 TPS562243 , TPS562246

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Input and Output Connections
    2. 2.2 Output Voltage Setpoint
    3. 2.3 Start-Up Procedure
  8. 3Implementation Results
    1. 3.1 Test Setup and Results
      1. 3.1.1 Load Transient Response
      2. 3.1.2 Start-Up
      3. 3.1.3 Shutdown
      4. 3.1.4 Output Voltage Ripple
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6Reference

4.2 PCB Layout

Figure 5-2, Figure 5-3, and Figure 5-4 show the board layout for the TPS562243EVM. The top layer contains the main power traces for VIN, VOUT, and ground. Connections for the pins of the TPS562243 and a large area filled with ground are also on the top layer. Most of the signal traces are also located on the top side. The input decoupling capacitors C1, C2, and C3 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the signal ground copper fill and the feedback trace from the point of regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2-oz copper thickness.

GUID-20240403-SS0I-V5CP-9CBF-JDSDDP04TQT0-low.svgFigure 4-2 TPS562243EVM Top Assembly
GUID-20240403-SS0I-S7PS-KP0C-XRG3NQ86NPDN-low.svgFigure 4-4 TPS562246EVM Bottom Layer
GUID-20240403-SS0I-VMHD-CSG7-5W891ZLHJBCK-low.svgFigure 4-3 TPS562243EVM Top Layer