The device is enabled once the voltage at the EN pin trips its threshold and the input voltage is above the UVLO threshold. The TPS62120 stops operation once the voltage on the EN pin falls below its threshold or the input voltage falls below the UVLO threshold.

Because V_OUT is the IC ground in this configuration, the EN pin must be referenced to V_OUT instead of ground. In the buck configuration, 1.1 V is considered a high and less than 0.4 V is considered a low. In the inverting buck-boost configuration, however, the V_OUT voltage is the reference; therefore, the high threshold is 1.1 V + V_OUT and the low threshold is 0.4 V + V_OUT. For example, if V_OUT = –5 V, then V_EN is considered at a high level for voltages above -3.9 V and a low level for voltages below –4.6 V.

This behavior can cause difficulties enabling or disabling the part, since in some applications, the IC providing the EN signal may not be able to produce negative voltages. The level shifter circuit shown in Figure 2-1 alleviates any difficulties associated with the offset EN threshold voltages by eliminating the need for negative EN signals. If disabling the TPS62120 is not desired, the EN pin may be directly connected to V_IN without this circuit.

VOUT is the negative output voltage of the inverting buck-boost converter

Figure 2-1 EN Pin Level Shifter

The positive signal that originally drove EN is instead tied to the gate of Q1 (SYS_EN). When Q1 is off (SYS_EN grounded), Q2 sees 0 V across its V_GS, and also remains off. In this state, the EN pin sees –5 V which is below the low-level threshold and it disables the device.

When SYS_EN provides enough positive voltage to turn Q1 on (V_GS threshold as specified in the MOSFET datasheet), the gate of Q2 sees ground through Q1. This drives the V_GS of Q2 negative and turns Q2 on. Now, V_IN ties to EN through Q2 and the pin is above the high-level threshold, turning the device on. Be careful to ensure that the V_GD and V_GS of Q2 remain within the MOSFET ratings during both the enabled and disabled states. Failing to adhere to this constraint can result in damaged MOSFETs.

The enable and disable sequence is illustrated in Figure 2-2 and Figure 2-3. The SYS_EN signal activates the enable circuit, and the GD Node signal represents the shared node between Q1 and Q2. This circuit was tested with a 1.8-V SYS_EN signal and dual N/PFET Si1029X. The EN signal is the output of the circuit and goes from V_IN to –V_OUT properly enabling and disabling the device. The SGND pin was used to accelerate V_OUT’s return to 0 V, when the IC is disabled.

Figure 2-2 Enable Sequence

Figure 2-3 Disable Sequence