SLVA478C October   2013  – November 2022 TPS62120 , TPS62122

 

  1.   Using the TPS62120 in an Inverting Buck-Boost Topology
  2.   Trademarks
  3. 1Inverting Buck-Boost Topology
    1. 1.1 Design Considerations
    2. 1.2 Concept
    3. 1.3 Output Current Calculations
    4. 1.4 VIN and VOUT Range
  4. 2Digital Pin Configurations
    1. 2.1 Enable Pin
    2. 2.2 SGND Pin
    3. 2.3 Power Good Pin
  5. 3Startup Behavior and Switching Node Consideration
  6. 4External Component Selection
    1. 4.1 Inductor Selection
    2. 4.2 Input Capacitor Selection
    3. 4.3 Selecting L and COUT for Stability
  7. 5Typical Performance and Waveforms
  8. 6Conclusion
  9. 7References
  10. 8Revision History

3 Startup Behavior and Switching Node Consideration

Figure 3-1 shows the startup behavior in the inverting configuration. After EN is taken high, the device starts switching after about a 50-µs delay. Due to the higher peak currents in the inverting topology, current limit is frequently reached during startup. This is acceptable as long as the saturation current of the inductor is chosen appropriately.

GUID-B423542A-7D7E-4009-B60C-1E49E57B52E2-low.gifFigure 3-1 Startup Behavior in the Inverting Configuration

Figure 3-1 also shows the SW node voltage as the device starts up. The voltage on the SW pin switches from VIN to VOUT. As the high-side MOSFET turns on, the SW node sees the input voltage and as the low-side MOSFET turns on, the SW node sees the IC ground, which is the output voltage. As VOUT continues to ramp down, the SW node low level follows it down.