SLVAE87A December   2020  – October 2023 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 NPN LDO Supply
  5. 2 AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM
    1. 2.1 Base Device
    2. 2.2 Design Summary
  6. 3 OTP Programming
  7. 4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)
    1. 4.1 Cell Voltage Sense (VCn)
    2. 4.2 Cell Balancing (CBn)
      1. 4.2.1 Non-Adjacent Cell Balancing
      2. 4.2.2 Adjacent Cell Balancing
      3. 4.2.3 Cell Balancing With External FET
    3. 4.3 Using Fewer Than 16 Cells
      1. 4.3.1 Design Summary
  8. 5 Bus Bar Support
    1. 5.1 Bus Bar on BBP/BBN
    2. 5.2 Typical Connection
      1. 5.2.1 Cell Balancing Handling
    3. 5.3 Bus Bar on Individual VC Channel
    4. 5.4 Multiple Bus Bar Connections
      1. 5.4.1 Two Bus Bar Connections to One Device
      2. 5.4.2 Three Bus Bar Connections to One Device
      3. 5.4.3 Cell Balancing Handling
  9. 6 TSREF
  10. 7 General Purpose Input-Output (GPIO) Configurations
    1. 7.1 Ratiometric Temperature Measurement
    2. 7.2 SPI Mode
      1. 7.2.1 Support 8 NTC Thermistors With SPI Slave Device
      2. 7.2.2 Design Summary
  11. 8 Base and Bridge Device Configuration
    1. 8.1 Power Mode Pings and Tones
      1. 8.1.1 Power Mode Pings
      2. 8.1.2 Power Mode Tones
      3. 8.1.3 Ping and Tone Propagation
    2. 8.2 UART Physical Layer
      1. 8.2.1 Design Considerations
  12. 9 Daisy-Chain Stack Configuration
    1. 9.1 Communication Line Isolation
      1. 9.1.1 Capacitor Only Isolation
      2. 9.1.2 Capacitor and Choke Isolation
      3. 9.1.3 Transformer Isolation
      4. 9.1.4 Design Summary
    2. 9.2 Ring Communication
    3. 9.3 Re-Clocking
      1. 9.3.1 Design Summary
  13. 10Multi-Drop Configuration
  14. 11Main ADC Digital LPF
  15. 12AUX Anti Aliasing Filter (AAF)
  16. 13Layout Guidelines
    1. 13.1 Ground Planes
    2. 13.2 Bypass Capacitors for Power Supplies and References
    3. 13.3 Cell Voltage Sensing
    4. 13.4 Daisy Chain Communication
  17. 14BCI Performance
  18. 15Common and Differential Mode Noise
    1. 15.1 Design Consideration
  19. 16Revision History

8.2 UART Physical Layer

The device can operation as a standalone device such as in a multidrop configuration (DEV_CONF[MULTIDROP_EN] = 1) or as a base/stack device in a daisy chain configuration (DEV_CONF[MULTIDROP_EN] = 0). In multidrop configuration, the daisy chain communication is disabled and the host communicates only with a single device through the UART interface. This chapter will introduce UART interface configuration focusing on daisy chain communication.

The UART sends data on the TX pin and receives data on the RX pin. When idle, the TX and RX are high. The UART interface requires that RX is pulled up to CVDD through a 100-kΩ resistor on the base device. The RX shall be pulled up on the BQ79616 side. Do not leave RX unconnected. Ensure RX is connected directly to CVDD for stack devices.

TX is disabled in stack devices, but must be pulled high through a 100-kΩ resistor on the host side on the base device to prevent triggering an invalid communication frame when the communication cable is not attached, or during power-off or SHUTDOWN state when TX is high impedance. TX is always pulled to CVDD internally while in ACTIVE or SLEEP mode, whether enabled or disabled. Leave TX unconnected if not used in stack devices. NFAULT is an active low fault indicator that, in the event of a fault, will pull low to signal to the host that a fault has occurred. Due to this fact the NFAULT pin should have a 100-kΩ pullup resistor to CVDD. If the device is a stack device then NFAULT can be left unconnected.

Refer to Table 8-1 for information on base device communication using a digital isolator.

Table 8-1 UART Physical Layer Check List
List Pin Base Device Stacked Devices Top of Stack Device
1 RX 100 kΩ pullup to CVDD, 51 pF to GND CVDD CVDD
2 TX 100 kΩ pullup on Host side Float Float
3 COMML+ COMMH+ of Top of Stack COMMH+ of lower device COMMH+ of lower device
4 COMML– COMMH+ of Top of Stack COMMH– of lower device COMMH– of lower device
5 COMMH+ COMML+ of upper device COMML+ of upper device COMML+ of Base Device
6 COMMH– COMML– of upper device COMML– of upper device COMML- of Base Device
7 NFAULT 100 kΩ pullup to CVDD Float Float