SLVAE87A December   2020  – October 2023 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 NPN LDO Supply
  5. 2 AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM
    1. 2.1 Base Device
    2. 2.2 Design Summary
  6. 3 OTP Programming
  7. 4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)
    1. 4.1 Cell Voltage Sense (VCn)
    2. 4.2 Cell Balancing (CBn)
      1. 4.2.1 Non-Adjacent Cell Balancing
      2. 4.2.2 Adjacent Cell Balancing
      3. 4.2.3 Cell Balancing With External FET
    3. 4.3 Using Fewer Than 16 Cells
      1. 4.3.1 Design Summary
  8. 5 Bus Bar Support
    1. 5.1 Bus Bar on BBP/BBN
    2. 5.2 Typical Connection
      1. 5.2.1 Cell Balancing Handling
    3. 5.3 Bus Bar on Individual VC Channel
    4. 5.4 Multiple Bus Bar Connections
      1. 5.4.1 Two Bus Bar Connections to One Device
      2. 5.4.2 Three Bus Bar Connections to One Device
      3. 5.4.3 Cell Balancing Handling
  9. 6 TSREF
  10. 7 General Purpose Input-Output (GPIO) Configurations
    1. 7.1 Ratiometric Temperature Measurement
    2. 7.2 SPI Mode
      1. 7.2.1 Support 8 NTC Thermistors With SPI Slave Device
      2. 7.2.2 Design Summary
  11. 8 Base and Bridge Device Configuration
    1. 8.1 Power Mode Pings and Tones
      1. 8.1.1 Power Mode Pings
      2. 8.1.2 Power Mode Tones
      3. 8.1.3 Ping and Tone Propagation
    2. 8.2 UART Physical Layer
      1. 8.2.1 Design Considerations
  12. 9 Daisy-Chain Stack Configuration
    1. 9.1 Communication Line Isolation
      1. 9.1.1 Capacitor Only Isolation
      2. 9.1.2 Capacitor and Choke Isolation
      3. 9.1.3 Transformer Isolation
      4. 9.1.4 Design Summary
    2. 9.2 Ring Communication
    3. 9.3 Re-Clocking
      1. 9.3.1 Design Summary
  13. 10Multi-Drop Configuration
  14. 11Main ADC Digital LPF
  15. 12AUX Anti Aliasing Filter (AAF)
  16. 13Layout Guidelines
    1. 13.1 Ground Planes
    2. 13.2 Bypass Capacitors for Power Supplies and References
    3. 13.3 Cell Voltage Sensing
    4. 13.4 Daisy Chain Communication
  17. 14BCI Performance
  18. 15Common and Differential Mode Noise
    1. 15.1 Design Consideration
  19. 16Revision History

4.2.1 Non-Adjacent Cell Balancing

Auto balancing control is configured by setting [AUTO_BAL] = 1. In auto balancing control mode, CBFETs are enabled in an odd and even sequence.

GUID-333B1E91-09BC-426D-A1CC-27BF3812F5A4-low.jpg Figure 4-2 Internal CB Diagram (no adjacent cell balancing)

Figure 4-2 shows the cell balancing current path. Cell balancing current (ICB ) is dependent on cell voltage (VCELL) and the resistance of the balancing path (2 × RCB+ RDS(ON)). The equation is shown in Equation 2. RCB is the series resistor. RDS(ON) is the resistance of the internal FET when it is on. The higher the total resistance of the path, the lower the cell balancing current that flows.

To get a target cell balancing current, RCB can be chosen by following two steps.

Step 1 : Select RCB value

The RCB value can be calculated considering the desired cell balancing current at the highest RDS(ON) at the highest operating temperature using the equation in Equation 3.

Step 2 : Calculate RCB power rating

Power rating for RCB can be calculated with the highest cell balancing current at the minimum RDS(ON). An example calculation for how to select the value of RCB and power rating to get the desired cell balancing current is shown in Figure 4-3.

Equation 2. I C B   =   V C E L L R D S ( O N )   +   2 × R C B
Equation 3. R C B   =   1 2   V B A T I C B   -   R D S ( O N )
GUID-E0124556-CF5E-479C-96AB-D2F7A15C470E-low.jpg Figure 4-3 Cell Balancing Resistor Example Calculation

Passive balancing dissipates heat to the die, increasing the die temperature as balancing current increases. Refer to the BQ79616-Q1 data sheet for the recommended maximum balancing current according to the ambient temperature.