SLVAEK9A December   2019  – November 2020 TPS62160-Q1 , TPS62162-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 Pin Failure Mode Analysis for TPS62160-Q1
    2. 4.2 Pin Failure Mode Analysis for TPS62162-Q1
  6. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS62160-Q1 and TPS62162-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

The following tables also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
Class Failure Effects
A Potential device damage that affects functionality
B No device damage, but loss of functionality
C No device damage, but performance degradation
D No device damage, no impact to functionality or performance

Figure 4-1 shows the TPS62160-Q1 and TPS62162-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPS62160-Q1 and TPS62162-Q1 data sheet.

GUID-13C2B888-BAF2-4AC5-8ACA-402D54FF8B6A-low.gif Figure 4-1 Pin Diagram