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The TPS2663 device incorporates protection features such as inrush current management, adjustable overcurrent limit, short-circuit protection, overvoltage and input reverse polarity protection. Figure 1-1 shows an application schematic of the TPS26631 feeding a downstream DC-DC converter in a PLC system. The capacitor CdVdT on the dVdT pin sets the output voltage slew-rate and hence the inrush current level where as the resistor RILIM sets the current limit (ILIM) which the device needs to limit to under fault conditions. The device offers a B-FET driver to control an external N-channel FET ‘Q1’ for reverse current and reverse polarity protection which simplifies designs requiring class-A performance during system tests like IEC61000-4-5 surge tests as well as input supply brown-out tests.
The maximum current the TPS2663 can support is up to 6 A. However the device can be used in parallel configuration with multiple TPS2663 devices to achieve higher output currents which is often required in many industrial systems. This report presents how the TPS2663 can be used in parallel operation to achieve higher output currents as well as to demonstrate the performance benefits it brings to the system with its integrated protection functions.
The basic principle of eFuse parallel operation and the design considerations are covered in the Achieve 20-A Circuit Protection and Space Efficiency Using Paralleled eFuses Application Report(1). The same concept is applicable for TPS26631 parallel operation. The key points from the Achieve 20-A Circuit Protection and Space Efficiency Using Paralleled eFuses Application Report(1) are summarized in the rest of this section in the context of TPS26631.
Figure 2-1 illustrates the circuit configuration of two TPS26631 devices in parallel. A single blocking FET Q1 on the primary eFuse is enough for reverse current blocking. Figure 2-2 shows the current sharing during start-up with dVdT pins together. Even though the ramp rate of the dVdT pin is the same for both the devices, the mismatch in the internal dVdT gain and the internal FET characteristics leads to unequal current sharing during start-up. For uniform current distribution while starting up into large loads, current limited start-up is recommended as follows
The modified parallel circuit configuration is illustrated in Figure 2-3 and the corresponding start-up waveform demonstrating equal start-up current between two TPS26631 devices is shown in Figure 2-4. In this application report, RILIM resistor switch network is considered in the design example as it ensures uniform current sharing under all the stressful events.
An example of designing four TPS26631 eFuse parallel circuits is considered in this section.
Table 3-1 shows the design parameters for this application example.
Design Parameter | Example Value |
---|---|
Typical input voltage, VIN | 24 V |
Undervoltage lockout set point, VUV | 18 V |
Overvoltage cutoff set point, VOV | 33 V |
Inrush current limit, IINRUSH | 2.4 A |
Maximum load current, IOUT | 22 A |
IEC61000-4-5 Surge test level | ±500 V with 2-Ω generator impedance |
Surge performance | Class-A |
In this example, the TPS26631
variant is considered to highlight the current sharing during the 2 × pulse
current support. For more information, see the Device Comparison
Table in the TPS2663x 60-V, 6-A Power Limiting, Surge
Protection Industrial eFuse data sheet for device
selection. In a system where reverse current blocking is not required, the
TPS1663 devices are recommended.
To limit the inrush current
to 2.4 A (that is, 0.6 A per device), the RLIM_Low is selected as
30 kΩ. Considering the cumulative current limit accuracy of 10% and to
support maximum load current of 22 A, the current limit is set at 24 A (that
is, 6 A per device). This results in 3.33-kΩ value for
RLIM_High.
The resistors R1, R2, and R3 are selected as 887 kΩ, 29.4 kΩ, and 34 kΩ,
respectively, to set 18 V as undervoltage lockout and 33 V as overvoltage
trip point.
Leave dVdT pins OPEN because
the RILIM resistor switch network is considered in this
design.
In parallel configuration, IMON pins of all the devices can be combined to monitor the total system current. The maximum value of the RIMON resistor can be determined by Equation 1. The maximum VIMON voltage is determined by the ADC input range and it is 3.3 V.
Where GAINIMON is 27.9 µA/A (typ) and IOUT_max is 48 A because of 2 × overcurrent pulse support with the TPS26631.
Using Equation 1, we get RIMON as 2.46 kΩ.
The output of these pins are
used only from the primary eFuse to control downstream load and these pins
are left OPEN for the rest of the parallel TPS26631 devices.
The TPS2663 device uses PGTH as the output load voltage monitor and to set the downstream loads UVLO threshold. The voltage at PGTH determines the way the TPS2663 recovers during the system faults. During the fault recovery instance, if the V(PGTH) level is above V(PGTHF), then the internal FET turns ON with a fast slew rate to meet Class-A system performance during surge events with optimal output buffer capacitance.
Typically, the minimum operating voltage of the DC-DC converter designed for 24-V rail is at 15 V. Assuming UVLO to be at 20% lower level, VUVLO_DC-DC = 12 V. Use Equation 2 to calculate R4 and R5.
V(PGTHF) = 1.14 V. Assuming R5 = 56 kΩ,
R4 comes out to be approximately 499 kΩ.
During the surge event TSURGE, the output capacitor COUT of the TPS2663 provides energy to the load. The COUT should be selected such that the output voltage does not drop below VUVLO_DC-DC during TSURGE interval. Use Equation 3 to compute the required buffer capacitor COUT:
where
The value is determined
to be COUT = 2.85 mF. Choose a capacitor with ±10% tolerance,
COUT = 3 mF / 35 V electrolytic capacitor.
A minimum of
0.1-µF ceramic decoupling capacitor is recommended at the input and the
output for each of the eFuse.
Choose at least a
80-V rated N-channel FET. Two CSD19532Q5B FETs are used in parallel to
support continuous load current of 22 A.
For clamping ±500-V, 2-Ω surge voltages with in the absolute maximum voltage rating of the TPS2663 device, bidirectional TVS diode SMCJ36CA is used at the input. Similarly, to clamp the negative voltages at the output during fast turn-off events, a Schottky diode B560C-13-F is recommended at the output.
Figure 3-1 shows the PCB with four TPS26631 devices.
Table 4-1 details the comparison between the solutions.
Parameter | LM5069 and LM5050 Based Solution | TPS2663 Parallel Configuration | Comments |
---|---|---|---|
Input voltage range | 9 V to 80 V, 100 V absolute maximum | 4.5 V to 60 V, 67 V absolute maximum | Higher absolute maximum voltage rating of LM5069 and LM5050 provides flexibility in high voltage applications. |
Driving large capacitive loads | Yes, using dv/dt
soft-start circuit at the GATE of LM5069 |
Yes |
The thermal regulation loop in the TPS2663 helps to charge unknown capacitive loads as detailed in the Reliable Startup with Large and Unknown Capactive Loads Application Report. |
MOSFET SOA protection | Yes, through the internal FET power-limiting scheme | Yes, through the internal thermal regulation loop and overtemperature protection | Integration offers accurate FET temperature measurement and reliable protection. External FET solution with the LM5069 always overdesigned to account “factor of safety” for FET SOA. |
Current limiting (accuracy %) | Yes, (±11.8%) | Yes, (±7%) | Better current limit accuracy with the TPS2663 helps to optimize the input supply size or rating |
Current monitoring | No | Analog current monitor output with ±6% | |
Surge protection | Provides only Class-B system performance | The fast recovery feature in the TPS2663 helps to achieve Class-A system performance | The LM5069 solution requires large capacitance at the output to buffer the load during surge, power interruptions for meeting Class-A system performance |
Supply line transients | Supply line transients cause false trips and often needs trade-off between immunity and short-circuit response | The smart control scheme in the TPS2663 distinguishes real faults from system transients and provides immunity to the transients | |
Fault status | No | Yes | Fault status output helps to monitor the system status |
No. of components |
ICs: LM5069, LM5050 Hot-swap
FET: CSD19502Q5B ORing FETs:
2 × CSD19532Q5B RSENSE: 2 mΩ, 1.5 W COUT: 7 ×
2.2 mF, |
ICs: 4 ×
TPS26631 ORing
FETs: COUT: 3 × 1
mF, |
Only the critical space occupying components are considered. The LM5069 solution requires large output capacitance to meet Class-A system performance. |
Solution size | 2924 mm2 | 1323 mm2 |
55% reduction in solution size |
Figure 5-1 shows the parallel circuit configuration for TPS16630 devices. In this circuit, dv/dt start-up is considered, assuming that the system uses a large CdVdT value of > 470 nF where the mismatch in start-up currents between the devices is low. If equal current sharing during start-up is preferred, use the RILIM switch network at the ILIM pin of each device as discussed in Section 2 for TPS2663 device.
The TPS2663 parallel configuration helps to scale up the circuit protection to higher current levels. This approach facilitates a reliable and space-efficient high-current protection solution with the inherent ability to meet Class-A system performance. The additional benefits of accurate current limiting and immunity to system transients with the TPS2663 device clearly outpaces the legacy hot-swap and ORing controllers based solutions.
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