SLVAFD0B may 2022 – september 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , TPS65219 , TPS65219-Q1 , TPS65220
The TPS65219 power-up sequence is gated by the following main steps: Voltage on VSYS goes above the POR_Rising threshold, PMIC loads the NVM content into the register map and then waits for an ON request before executing the power-up sequence. The first ON request can be bypassed by enabling the first supply detection feature (FSD) in the PU_ON_FSD register field. When PU_ON_FSD=0x1, PMIC starts executing the power-up sequence after the NVM settings are loaded to the register map, without waiting for an ON request. In this scenario, customers must ensure the pre-regulator supplying the VSYS reaches a stable output voltage before the PMIC starts executing the power-up sequence. The voltage on VSYS must reach the targeted Vout in approximately 2.3ms after VSYS goes above the POR_threshold.
Figure 6-1 shows an example where FSD is enabled and VSYS has a slow ramp.
Figure 6-2 shows an example where FSD is disabled and VSYS has a slow ramp.