2 Ensuring FET SOA in Hot-Swap Design

Since mechanism to limit external FET junction temperature is not present in traditional hot-swap design, external FET SOA operation is made sure by system designer. First, external FET, power limit, and fault timer are selected. The next task for the designer is to verify FET SOA by calculations and do necessary iterations on the power limit and fault timer values. Once the power limit and fault timer are chosen, critical requirement to check is that the FET will stay within its SOA during all the stressful conditions. Please refer to Section 3.1 in the Robust Hot Swap Design application note for step-by-step design procedure and FET SOA verification in a traditional hot-swap design.

For example, during a Hot-Short the circuit breaker trips and the LM5066I re-start into power limit until the timer runs out. In the worst case, the MOSFET’s VDS equal (VINMAX), IDS equal (PLIM / VINMAX) and the stress event lasts for set fault time. The SOA for chosen fault timer duration can be extrapolated by approximating SOA vs time as a power function as shown in Robust Hot Swap Design application note. Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be much higher during a hot-short. The SOA has to be de-rated based on case temperature.

The following section describes how eFuse manages SOA of its integrated FET through robust protection mechanisms.