SLVAFP1 February 2024 TPS54KB20
This application report provides the recommended layout methods if users are seeking to utilize symmetrical input voltage rails or asymmetrical input voltage rails with a number of removed input capacitors. This report also provides bench data supporting each design, making the two layout methods easily comparable. The symmetrical butterfly footprint guarantees the minimum amount of SW-node ringing along with the highest efficiency compared to the asymmetrical design. Although the symmetrical layout is recommended, this document provides users with an alternative if a single input rail and capacitor reduction is essential. Having this alternate selection grants users with design flexibility. The TPS54KB2x utilizes the unique butterfly-style footprint with the capability of retaining a stable SW-node while granting users the option to remove the recommended amount of capacitors from one side of the package.
Table 6-1 lists a table summary for the recommended symmetrical and asymmetrical input capacitor configurations. The table specifies the number of VIN rails and input capacitors for each configuration method.
Layout Method | # of VIN Rails | CIN PIN 3 | CIN PIN 9 |
---|---|---|---|
Symmetrical | 2 | 3x10µF, 1x1µf, 1x0.1µF | 3x10µF, 1x1µf, 1x0.1µF |
Asymmetrical | 1 | 4x10µF, 1x1µf, 1x0.1µF | 0x10µF, 0x1µf, 1x0.1µF |