As discussed previously, a large value of bulk capacitance is desired to provide a constant motor supply voltage during current transitions, such as motor start-up, changes in load torque, or PWM operation. But we can like having a working estimate of the needed capacitance so that we do not over-design the bulk capacitance, leading to high system cost and excessive board size. We can use a general guideline method to find an appropriate capacitor size based on the expected load current variation and allowable motor supply voltage variation.

An initial estimate of the appropriate bulk capacitance based on ideal capacitors is:

Where C_BULK is the bulk capacitance, ΔI_MOTOR is the expected variation in motor current, T_PWM is the pulse-width modulation period, and ΔV_SUPPLY is the allowable variation in the motor supply voltage.

This inequality is based on assumptions:

• Ideal capacitors with zero equivalent series resistance (ESR)
• A motor time constant L_m/R_m significantly longer than the PWM period
• Negligible change in supply current through the parasitic wire inductance
• The supply voltage variation induced by the varying motor current during PWM can be expected to be a maximum when the PWM duty cycle is 50%.

In an example, assume we have motor current variation during PWM of about ΔI_MOTOR = 200mA; this is approximately what is shown in Figure 2-2; a simplified sketch is shown in Figure 2-4. For a typical PWM frequency of 20kHz, T_PWM is 50 microseconds.

Figure 2-4 Simplified Example Motor Current Waveform During PWM

If we want to keep the motor supply voltage variation not more than ΔV_SUPPLY = 100mV, we can estimate the required minimum bulk capacitance as:

This is an estimate, not a detailed analysis. We are neglecting several factors such as the effective series resistance (ESR) of the bulk capacitance, the non-infinite impedance of the inductance to the battery, the non-linear current variation shape, and so on. However, it gives a reasonable bulk capacitance value as a starting point for more rigorous system analysis.

In Figure 2-5 the results for the ideal simulations are compared to what is predicted by the ideal capacitor equations. The simulated voltage ripple is somewhat smaller than the ideal estimate predicts, but overall the predictions and simulations are approximately in alignment, especially for higher values of bulk capacitance.

Figure 2-5 Comparison of Ideal Capacitor (ESR=0) General Guideline and Simulated Results

However, as we see in the following discussion, real-life measurements indicate the ideal results are off by as much as a factor of 3, which means the non-ideal capacitance ESR cannot be neglected.