SLVAFU5 July   2024 LP87521-Q1 , LP87562-Q1 , LP87563-Q1 , TPS62811-Q1 , TPS745-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Design Parameters
  6. 3 Power Design
  7. 4 Sequencing
    1. 4.1 Startup
    2. 4.2 Shutdown
  8. 5 Schematic
  9. 6 Compatibility with X9HP
  10. 7 Software Drivers
  11. 8 Recommended External Components
  12. 9 Summary
  13. 10References

3 Power Design

Figure 3-1 and Figure 3-2 show the example block diagram of LP87562-Q1, LP87563-Q1, LP87521-Q1 and other discrete buck converters and LDOs powering the X9SP power rails. LM25149-Q1 is used as a pre-regulator to generate 5V input voltage for the PMICs and discrete buck converters and LDOs. LP87562-Q1, LP87563-Q1, LP87521-Q have the output voltages, sequencing etc. pre-programmed to the OTP memory. Please contact TI sales for details on the OTP settings.

Semidrive X9SP RTC and Safety Power Block Diagram Figure 3-1 Semidrive X9SP RTC and Safety Power Block Diagram

The main features include the following:

  • 5V supplied from pre-regulator
  • After the RTC devices are powered, the LDO TPS74501-Q1 PGOOD for VDDIO_RTC0V8 can set the signal RTC_RESET to high.
  • MCU (in this case Semidrive X9SP) can set SYS_PWR_ON high to initiate startup sequence for safety rails.
  • When the powering up for safety rails is complete, the LDO TPS74501-Q1 PGOOD for VDD_SAF_1V8 can set the signal SAFETY_RESET to high.
  • Both RTC_RESET and SAFETY_RESET are open-drain.
Semidrive X9SP AP Power Block Diagram Figure 3-2 Semidrive X9SP AP Power Block Diagram

The main features include the following:

  • 5V supplied from pre-regulator
  • After the devices are powered, the microcontroller can control the EN signals of LP87521-Q1, LP87562-Q1 and LP87563-Q1 using system control signals SYS_CTRL0 and SYS_CTRL1.
  • Startup delays are controlled internally in the LP87521-Q1, LP87562-Q1 and LP87563-Q1 logic and discrete LDO/Buck are controlled with LP87562-Q1 and LP87563-Q1 GPIO3. Section 3 has more details about the startup/shutdown sequence.
  • I2C can be used to read status registers and reset interrupts. Since interrupt lines are connected together, both PMIC fault registers need to be read or cleared in case of interrupt goes low.
  • All PMIC devices have dedicated I2C address so the devices can share the same I2C bus.
  • TPS628501-Q1 PGOOD signals act as nRESET signal for the SoC (AP_RESET). Note the PGOOD functionality is disabled in the PMIC configuration, although it can be enabled through I2C bus.