SLVAFW9 August   2024 LM51772

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Parallel or Multiphase Power Stages
    1. 2.1 Paralleling Power Stages
      1. 2.1.1 Load Balancing Requirement
    2. 2.2 Clock Generation
    3. 2.3 Interconnection of the Power Stages
  6. 3Application Implementation
    1. 3.1 Soft-start Capacitor
    2. 3.2 Compensation
    3. 3.3 Input and Output Capacitor
    4. 3.4 Usage of the Average Current Sensor
  7. 4Test Results
    1. 4.1 Load Current Balancing
    2. 4.2 Inductor Current
    3. 4.3 Thermal Images
      1. 4.3.1 Dual Phase Operation at Variable Load
      2. 4.3.2 Comparison Between Single Phase and Dual Phase Operation
  8. 5Summary
  9. 6References

4.1 Load Current Balancing

The test results of the relative error between 180° out-of-phase and in-phase load currents for different converter topologies is shown in Figure 4-1. The error is less than 10% when the total load current is above 2A for all input voltage conditions, but the buck-boost region (VIN = 20V) has the least relative error. Similarly, the test results of the load distribution of two phases under different input voltage conditions is shown in Figure 4-2. The load distribution between phases seems to be equal, but variation is seen among phases of different input voltage levels, especially for the high load currents.

Error of Load Currents with (IPhase1 - IPhase2)/ILoadFigure 4-1 Error of Load Currents with (IPhase1 - IPhase2)/ILoad
Load Distribution of the two PhasesFigure 4-2 Load Distribution of the two Phases