SLVAFZ0 November   2024 DRV8161 , DRV8162

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Three-Phase Gate Driver
    1. 2.1 Architecture
    2. 2.2 Layout Considerations
      1. 2.2.1 Advantages
        1. 2.2.1.1 MCU to DRV Signal Routing
        2. 2.2.1.2 Component Reduction
      2. 2.2.2 Challenges
        1. 2.2.2.1 MOSFET Placement
    3. 2.3 Typical Applications
  6. 3Half-Bridge (Single Phase) Gate Driver
    1. 3.1 Architecture
    2. 3.2 Layout Considerations
      1. 3.2.1 Advantages
        1. 3.2.1.1 MOSFET Placement
        2. 3.2.1.2 Independent Control
        3. 3.2.1.3 Ease of Replacement
      2. 3.2.2 Challenges
        1. 3.2.2.1 Longer Routing Between Gate Driver and Micro Controller
        2. 3.2.2.2 Additional Component Requirements
    3. 3.3 Typical Applications
  7. 4Summary
  8. 5References

3.2.1.1 MOSFET Placement

With the availability of three separate half-bridges you now have the option to place the IC close to the MOSFETs for that phase. This improves signal integrity and reduces parasitics on the gate and source nodes.

  • Source node transients or ringing:

    Shorter gate or source paths between the driver and the MOSFET can help dampen the effects of trace inductance. This can help reduce the effects of source node ringing and improve EMI performance by effectively decreases the total loop inductance.

    With lower effects of parasitics, you can also expect to see smaller source dips or transients. Figure 3-2 shows the ringing one can see at phase voltage switching

Motor Driver Phase Output Waveform Showing RingingFigure 3-2 Motor Driver Phase Output Waveform Showing Ringing
  • Signal Integrity:

    Any signal from the motor power stage that gets measured from the driver can offer benefits when the path between the origin of the signal to the measurement site gets reduced (Figure 3-3).

    Current flow being sensed by the driver across the shunt resistor can be more accurate since the CSA is physically closer to the sense resistor.

    Similarly, the VDS measurement for overcurrent protection is measured at the driver gate and source pins. So, if there is a large difference in drain to source between the driver and the FET, the VDS monitor is not accurate. Therefore, having the MOSFET and driver closer can result in smaller parasitic inductance helping reduce overshoot or ringing of gate signal.

    Impact of MOSFET placement on signal integrity Figure 3-3 Impact of MOSFET placement on signal integrity
Note: In Figure 3-3, L1 and L2 can be much lower inductance than L3 and L4 due to smaller trace length. L3 and L4 can also be more susceptible to other signal coupling in along the long trace.