8 Single-Event Transients (SET)

SET are defined as heavy-ion-induced transients upsets on the OUTX, SRX, SS, and Error Amp (while in unity gain) of the TPS7H500x-SP.

Testing was performed at room temperature (no external temperature control applied). The heavy-ions species used for the SET testing were Krypton (⁸⁴Kr), Silver (¹⁰⁹Ag), Praseodymium (¹⁴¹Pr), and Holmium (¹⁶⁵ Ho) for an LET_EFF = 30 to 75 MeV·cm²/mg. For more details, see Ion LET_EFF, Depth, and Range in Silicon. Flux of 7.75 × 10⁴ to 1.65 × 10⁵ ions/cm²·s and a fluence of 9.97 × 10⁶ to 1 × 10⁷ ions/cm², per run were used for the SET characterization.

SET testing was categorized as:

1. V_IN = 12 V (nominal) at F_SW = 500 kHz
   

   (All TPS7H500X-SP devices)

   .
2. V_IN = 14 V (max) at F_SW = 500 kHz.
3. V_IN = 4 V at F_SW = 500 kHz.
4. Error amplifier.
5. Cross conduction at F_SW = 500 kHz.
6. V_IN = 4 V (min) at F_SW = 500 kHz using an external clock with R_T = open.
7. V_IN = 14 V (max) at F_SW = 500 kHz using an external clock with R_T = open.
8. V_IN = 4 V (min) 12 V (nominal) and 14 V (max) at F_SW = 1 MHz using the internal clock with R_T = 90.9 kΩ.
9. V_IN = 4 V (min) 12 V (nominal) and 14 V (max) at F _SW= 2 MHz using the internal clock with R_T = 38.3 kΩ.

As the list shows, the only SET case that was repeated for the TPS7H5002/3/4-SP devices was the 12-V nominal at F_SW = 500 kHz case. All other SET cases were conducted with the TPS7H5001-SP. This was done due to how closely the TPS7H5002/3/4 devices correlated SET wise to the original TPS7H5001-SP device, specifically having similar number of OUTA and SRB transients and the same found onset.

Cross conduction is a concern in synchronous converter applications due to the possibility of a short circuit during an SET upset. In addition to the hardware X-conduction testing, all recorded upsets during all runs discussed on this report (SEL, SEB, and SET) were verified for such conditions when possible. Using software, cross conduction was verified for:

1. OUTA to SRA.
2. OUTB to SRB.
3. OUTA to OUTB.

The PWM signals were converted to digital levels by comparing the voltage levels of the recorded upset to an V_IH = 1.89 V (V_IH from the LMG1205 GaN driver was used). If the signals were greater than this voltage, a digital one was returned. Otherwise, a logical 0 was recorded. After the signals were converted into a digital value array, a BITAND was implemented using the desired waveforms. If any logical 1 was present on the resulting response, a cross conduction was said to occur. Not a single upset of this kind was recorded across all upsets and all runs including SEL, SEB, and SET.

Table 8-1 shows waveform size, sample rate, trigger type, value, and signal for all scopes used. For SS, not a single capture was recorded under the conditions used for the data collection. For this reason, the data is not presented in the table.

V_IN = 12 V (Nominal) at F_SW = 500 kHz

For V_IN = 12 V and switching frequency of 500 kHz, the results are presented in Table 8-4. The outside-pulse width trigger was set to 30% from the nominal pulse width for both the DPO7104C and the PXIe-5110. Upper-bound cross section at 95% confidence interval and based on SLVK047 are presented in Table 8-3 and Table 8-4. The cross-section plot for this case and Weibull parameter are shown in Figure 8-1 and Table 8-5, respectively. A typical time domain plot for OUTA is shown in Figure 8-2. Since the main concern for a DC-DC converter is the OUTX, (OUTA and OUTB have similar if not equal performance), the OUTA signal was used to characterize the Onset. Due to SRX performing worse behavior than OUTX, the onset was not found during testing. To accurately determine the onset for SRX, a Weibull fit plot was created. Conditions and the Weibull fit plot for SRB are shown below with the remaining 12-V 500-kHz results.

Upper and lower bound were calculated to 95% confidence. Weibull fit was done for the mean value.

Figure 8-1 Cross Section and Weibull Fit for SRB at V_IN = 12 V and F_SW= 500 kHz

Figure 8-2 Worst Case OUTA Time Domain Upset (Run Number 14)

Figure 8-3 OUTA Normalized Percentage Pulse Width Deviation During Trigger

Figure 8-4 OUTA Duration of Triggers (µs)

Figure 8-5 Worst Case SRB Time Domain Upset (Run Number 14)

Figure 8-6 SRB Normalized Percentage Pulse Width Deviation During Trigger

Figure 8-7 SRB Duration of Triggers (µs)

V_IN= 14 V (Maximum) at F_SW= 500 kHz

V_IN=4-V (Min) at F_SW = 500 kHz

Error Amp in Unity Gain

Time Domain Plots for the COMP voltage and Normalized max Value for each upset is shown on Nominal Trigger on COMP Run Number 43 V_IN = 12 V

Figure 8-8 Nominal Trigger on COMP Run Number 43 V_IN = 12 V

Figure 8-9 Comp Peak Percentage Deviation from Nominal of Triggers

Cross-Conduction (Using Hardware) at F_SW = 500 kHz

For cross conduction using hardware an AND Gate (model: SN74AHCT1G08DCKR) was used. IN1 was set as OUTA and IN2 was used as SRA. The output of the AND gate was connected to the CH number 1 of the DPO7104C with an edge trigger at 2.5 V. Not a single trigger was capture indicating that the TPS7H500x-SP is cross-conduction free at the conditions tested and presented here. As mention in the SET introduction, all recorded upset were also verified for the cross conduction in software and not a single cross conduction upset was recorded.

F_SW = 500 kHz using an External Clock with R_T = Open

Figure 8-10 Worst Case OUTA Time Domain Upset (Run Number 48)

Figure 8-11 OUTA Normalized Percentage Pulse Width Deviation During Trigger With External Clock

Figure 8-12 OUTA Duration of Triggers (µs) With External Clock

Figure 8-13 Worst Case SRB Time Domain Upset (Run Number 48)

Figure 8-14 SRB Normalized Percentage Pulse Width Deviation During Trigger With External Clock

Figure 8-15 SRB Duration of Triggers (µs) With External Clock

F_SW = 1 MHz Using an Internal Clock with R_T = 90.9 kΩ

Figure 8-16 Worst Case OUTA Time Domain Upset (Run Number 57)

Figure 8-17 OUTA Normalized Percentage Pulse Width Deviation During Trigger With 1-MHz Internal Clock

Figure 8-18 OUTA Duration of Triggers (µs) With 1-MHz Internal Clock

Figure 8-19 Worst Case SRB Time Domain Upset (Run Number 57)

Figure 8-20 SRB Normalized Percentage Pulse Width Deviation During Trigger With 1-MHz Internal Clock

Figure 8-21 SRB Duration of Triggers (µs) With 1MHz Internal Clock

F_SW = 2 MHz Using an Internal Clock with R_T = 38.3 kΩ

Figure 8-22 Worst Case OUTA Time Domain Upset (Run Number 66)

Figure 8-23 OUTA Normalized Percentage Pulse Width Deviation During Trigger With 2-MHz Internal Clock

Figure 8-24 OUTA Duration of Triggers (µs) With 2-MHz Internal Clock

Figure 8-25 Worst Case SRB Time Domain Upset (Run Number 66)

Figure 8-26 SRB Normalized Percentage Pulse Width Deviation During Trigger With 2-MHz Internal Clock

Figure 8-27 SRB Duration of Triggers (µs) With 2-MHz Internal Clock