SLVK182 December   2024 DRV8351-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Device Information
    1. 1.1 Device Details
  5. 2Total Dose Test Setup
    1. 2.1 Test Overview
    2. 2.2 Test Description and Facilities
    3. 2.3 Test Setup Details
      1. 2.3.1 Bias Diagram
    4. 2.4 Test Configuration and Condition
  6. 3TID Characterization Test Results
    1. 3.1 TID Characterization Summary Results
    2. 3.2 Specification Compliance Matrix
  7. 4Reference Documents
  8. 5Appendix: HDR TID Report Data
  9. 6Appendix: ELDRS TID Report Data

3.2 Specification Compliance Matrix

Table 3-1 Electrical Parameters Table
ParameterTest ConditionsVCCTA = -55°C to +125°CUnitTest Name
MINTYPMAX
IGVDDGVDD standby mode current INHx = INLX = 0; VBSTx = VGVDD4008001500µAIGVDD_STANDBY
IGVDDGVDD active mode current INHx = INLX = Switching at 20kHz; VBSTx = VGVDD; NO FETs connected4008251500µAIGVDD_ACTIVE
ILBSxBootstrap pin leakage currentVBSTx = VSHx = 85V; VGVDD = 0V2713µAIL_BSX
ILBS_TRANBootstrap pin active mode transient leakage current INHx = Switching at 20kHz30105220µAIL_BSX_TRAN
ILBS_DCBootstrap pin active mode leakage static current INHx = High3085150µAIL_BSX_ACT
ILSHxHigh-side source pin leakage current INHx = INLX = 0; VBSTx - VSHx = 12V; VSHx = 0 to 85V305590µAIL_SHX_TRAN
VILInput logic low voltageINLx, INHx pins0.8VVIL_INHX
IILINHx, MODE Input logic low currentVPIN (Pin Voltage) = 0V-101µAIIL_INHX
IIHINHx, MODE Input logic high currentVPIN (Pin Voltage) = 5V;52030µAIIH_INHX
RPD_INHxINHx Input pulldown resistanceTo GND120200280kΩRPD_INHX
VGHx_LOHigh-side gate drive low level voltageIGLx = -100mA; VGVDD = 12V; No FETs connected00.150.35VVGHX_LO
VGHx_HIHigh-side gate drive high level voltage (VBSTx - VGHx)IGHx = 100mA; VGVDD = 12V; No FETs connected0.30.61.2VVGHX_HI
VGLx_LOLow-side gate drive low level voltageIGLx = -100mA; VGVDD = 12V; No FETs connected00.150.35VVGLX_LO
VGLx_HILow-side gate drive high level voltage (VGVDD - VGHx)IGHx = 100mA; VGVDD = 12V; No FETs connected0.30.61.2VVGLX_HI
IDRIVEP_HSHigh-side peak source gate currentGHx-SHx = 12V 4007501200mAIDRIVE_HSX_SOURCE
IDRIVEN_HSHigh-side peak sink gate currentGHx-SHx = 0V 85015002100mAIDRIVE_HSX_SINK
IDRIVEP_LSLow-side peak source gate currentGLx = 12V 4007501200mAIDRIVE_LSX_SOURCE
IDRIVEN_LSLow-side peak sink gate currentGLx = 0V 85015002100mAIDRIVE_LSX_SINK
tPDInput to output propagation delayINHx, INLx to GHx, GLx; VGVDD  = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx70125180nsTPD_GLX_GT8 TPD_GHX_GT8
tPD_matchMatching propagation delay per phaseGHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD  = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx-30±430nsTPD_MATCH_GT8_LSX TPD_MATCH_GT8_HSX
tPD_matchMatching propagation delay phase to phaseGHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF;  VGVDD  = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx-30±430nsTPD_MATCH_PP_GT8_LS TPD_MATCH_PP_GT8_HS
tR_GLxGLx rise time (10% to 90%)CLOAD = 1000 pF;  VGVDD  = VBSTx - VSHx > 8V; SHx = 0V102450nsTRISE_GLX_GT8
tR_GHxGHx rise time (10% to 90%)CLOAD = 1000pF;  VGVDD  = VBSTx - VSHx > 8V; SHx = 0V102450nsTRISE_GHX_GT8
tF_GLxGLx fall time (90% to 10%)CLOAD = 1000pF; VGVDD  = VBSTx - VSHx > 8V; SHx = 0V51230nsTFALL_GLX_GT8
tF_GHxGHx fall time (90% to 10%)CLOAD = 1000pF; VGVDD  = VBSTx - VSHx > 8V; SHx = 0V51230nsTFALL_GHX_GT8
tDEADGate drive dead timeDT pin connected to GND150215280nsTDEAD_GND_CHX
VBOOTDBootstrap diode forward voltageIBOOT = 100µA0.450.70.85VVBSTD_FW100UA
VBOOTDBootstrap diode forward voltageIBOOT = 100mA22.33.1VVBSTD_FW100MA
VGVDDUVGate Driver Supply undervoltage lockout (GVDDUV)Supply rising4.454.64.7VVGVDD_UV_RISE
tGVDDUVGate Driver Supply undervoltage deglitch time51013µsTGVDD_UV_DG
tBSTUVBootstrap undervoltage deglitch time61022µsTBST_UV_DG
RBOOTDBootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT)IBOOT = 100mA and 80mA111525ΩRBSTD_DYN