SLVS861F august   2008  – june 2020 TPS40210-Q1 , TPS40211-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     4
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum On-Time and Off-Time Considerations
      2. 7.3.2  Current Sense and Overcurrent
      3. 7.3.3  Current Sense and Subharmonic Instability
      4. 7.3.4  Current Sense Filtering
      5. 7.3.5  Soft Start
      6. 7.3.6  BP Regulator
      7. 7.3.7  Shutdown (DIS/ EN Pin)
      8. 7.3.8  Control Loop Considerations
      9. 7.3.9  Gate Drive Circuit
      10. 7.3.10 TPS40211-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Setting the Oscillator Frequency
      2. 7.4.2 Synchronizing the Oscillator
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Duty Cycle Estimation
        2. 8.2.2.2  Inductor Selection
        3. 8.2.2.3  Rectifier Diode Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Current Sense and Current Limit
        7. 8.2.2.7  Current Sense Filter
        8. 8.2.2.8  Switching MOSFET Selection
        9. 8.2.2.9  Feedback Divider Resistors
        10. 8.2.2.10 Error Amplifier Compensation
        11. 8.2.2.11 R-C Oscillator
        12. 8.2.2.12 Soft-Start Capacitor
        13. 8.2.2.13 Regulator Bypass
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1.     69

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VOLTAGE REFERENCE
VFBFeedback voltage rangeTPS40210-Q1COMP = FB,
4.5 ≤ VDD ≤ 52 V		TJ = 25°C693700707mV
–40°C ≤ TJ ≤ 125°C686700714
TPS40211-Q1COMP = FB,
4.5 ≤ VDD ≤ 52 V		TJ = 25°C254260266
–40°C ≤ TJ ≤ 125°C250260270
INPUT SUPPLY
IDDOperating current4.5 ≤ VDD ≤ 52 V, no switching, VDIS < 0.81.52.5mA
2.5 ≤ VDIS ≤ 7 V1020μA
VDD < VUVLO(on), VDIS < 0.8530
UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO(on)Turnon threshold voltage44.254.5V
VUVLO(hyst)UVLO hysteresis140195240mV
Frequency line regulation4.5 ≤ VDD ≤ 52 V–20%7%
7 ≤ VDD ≤ 52 V–10%7%
VSLPSlope compensation ramp520620720mV
PWM
VVLYValley voltage1.2V
SOFT-START
VSS(ofst)Offset voltage from SS pin to error amplifier input1V
RSS(chg)Soft-start charge resistance320430600kΩ
RSS(dchg)Soft-start discharge resistance84012001600
ERROR AMPLIFIER
GBWPUnity gain bandwidth product(1)1.53.0MHz
AOLOpen loop gain(1)6080dB
IIB(FB)Input bias current (current out of FB pin)100300nA
ICOMP(src)Output source currentVFB = 0.6 V, VCOMP = 1 V100250μA
ICOMP(snk)Output sink currentVFB = 1.2 V, VCOMP = 1 V1.22.5mA
OVERCURRENT PROTECTION
VISNS(oc)Overcurrent detection threshold (at ISNS pin)4.5 ≤ VDD < 52 V, –40°C ≤ TJ ≤ 125°C120150180mV
DOCOvercurrent duty cycle(1)2%
VSS(rst)Overcurrent reset threshold voltage (at SS pin)100150350mV
CURRENT-SENSE AMPLIFIER
ACSCurrent sense amplifier gain4.25.67.2V/V
IB(ISNS)Input bias current13μA
DRIVER
IGDRV(src)Gate driver source currentVGDRV = 4 V, TJ = 25°C375400mA
IGDRV(snk)Gate driver sink currentVGDRV = 4 V, TJ = 25°C330400
LINEAR REGULATOR
VBPBypass voltage output0 mA < IBP < 15 mA789V
DISABLE AND ENABLE
VDIS(en)Turn-on voltage0.71.3V
VDIS(hys)Hysteresis voltage25130220mV
RDISDIS pin pulldown resistance0.71.11.5MΩ
(1) Specified by design