SLVS927F March   2009  – July 2018 TPS65023-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      2. 8.3.2 Soft Start
      3. 8.3.3 Active Discharge When Disabled
      4. 8.3.4 Power-Good Monitoring
      5. 8.3.5 Low-Dropout Voltage Regulators
      6. 8.3.6 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 VRTC Output and Operation With or Without Backup Battery
      2. 8.4.2 Power-Save Mode Operation (PSM)
      3. 8.4.3 Low-Ripple Mode
      4. 8.4.4 100% Duty-Cycle Low-Dropout Operation
      5. 8.4.5 System Reset and Control Signals
        1. 8.4.5.1 DEFLDO1 and DEFLDO2
        2. 8.4.5.2 Interrupt Management and the INT Pin
    5. 8.5 Programming
      1. 8.5.1 Power-Up Sequencing
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register (address: 00h) Read-Only
      2. 8.6.2 PGOODZ Register (address: 01h) Read-Only
        1. Table 5. PGOODZ Register Field Descriptions
      3. 8.6.3 MASK Register (address: 02h)
      4. 8.6.4 REG_CTRL Register (address: 03h)
        1. Table 6. REG_CTRL Register Field Descriptions
      5. 8.6.5 CON_CTRL Register (address: 04h)
        1. Table 7. CON_CTRL Register Field Descriptions
      6. 8.6.6 CON_CTRL2 Register (address: 05h)
        1. Table 8. CON_CTRL2 Register Field Descriptions
      7. 8.6.7 DEFCORE Register (address: 06h)
        1. Table 9. DEFCORE Register Field Descriptions
      8. 8.6.8 DEFSLEW Register (address: 07h)
        1. Table 10. DEFSLEW Register Field Descriptions
      9. 8.6.9 LDO_CTRL Register (address: 08h)
        1. Table 11. LDO_CTRL Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Typical Characteristics

Table 1. EVM Parameters for Typical Characteristics Measurement(1)

CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE
VDCDC1 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF
VDCDC2 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF
VDCDC3 VLF4012AT-2R2M1R5 C2012X5R0J106M 2 × 10 μF
Graphs were taken using the evaluation module (EVM), TPS65023EVM-205, with the inductor and output capacitor combinations in Table 1. See TPS65023EVM, User's Guide for more information.

Table 2. Table Of Graphs

FIGURE
Efficiency vs Output current Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7
Output voltage vs Output current at 85°C Figure 8, Figure 9
Line transient response Figure 10, Figure 11, Figure 12
Load transient response Figure 13, Figure 14, Figure 15
VDCDC2 PFM operation Figure 16
VDCDC2 low ripple PFM operation Figure 17
VDCDC2 PWM operation Figure 18
Startup VDCDC1, VDCDC2 and VDCDC3 Figure 19
Startup LDO1 and LDO2 Figure 20
Line transient response Figure 21, Figure 22, Figure 23
Load transient response Figure 24, Figure 25, Figure 26
TPS65023-Q1 eff_5v_io1_lvs927.gifFigure 2. DCDC1: Efficiency vs Output Current
TPS65023-Q1 eff_18v_io1_lvs927.gifFigure 4. DCDC2: Efficiency vs Output Current
TPS65023-Q1 eff_18v_io3_lvs927.gifFigure 6. DCDC3: Efficiency vs Output Current
TPS65023-Q1 vo_io1_lvs927.gifFigure 8. DCDC2: Output Voltage vs Output Current At 85°C
TPS65023-Q1 vindcdc1_lvs927.gif
Figure 10. VDCDC1 Line Transient Response
TPS65023-Q1 vindcdc3_lvs927.gifFigure 12. VDCDC3 Line Transient Response
TPS65023-Q1 vdcdc2_ld_lvs927.gifFigure 14. VDCDC2 Load Transient Response
TPS65023-Q1 vdcdc2_vo1_lvs927.gifFigure 16. VDCDC2 Output Voltage Ripple
TPS65023-Q1 vdcdc2_vo3_lvs927.gifFigure 18. VDCDC2 Output Voltage Ripple
TPS65023-Q1 startup_ldo_lvs927.gifFigure 20. Startup LDO1 and LDO2
TPS65023-Q1 ldo2_lt_lvs927.gifFigure 22. LDO2 Line Transient Response
TPS65023-Q1 ldo1_ld_lvs927.gifFigure 24. LDO1 Load Transient Response
TPS65023-Q1 vrtc_ld_lvs927.gifFigure 26. VRTC Load Transient Response
TPS65023-Q1 eff_5v_io2_lvs927.gifFigure 3. DCDC1: Efficiency vs Output Current
TPS65023-Q1 eff_18v_io2_lvs927.gifFigure 5. DCDC2: Efficiency vs Output Current
TPS65023-Q1 eff_18v_io4_lvs927.gifFigure 7. DCDC3: Efficiency vs Output Current
TPS65023-Q1 vo_io2_lvs927.gifFigure 9. DCDC3: Output Voltage vs Output Current At 85°C
TPS65023-Q1 vindcdc2_lvs927.gifFigure 11. VDCDC2 Line Transient Response
TPS65023-Q1 vdcdc1_load_lvs927.gifFigure 13. VDCDC1 Load Transient Response
TPS65023-Q1 vdcdc3_ld_lvs927.gifFigure 15. VDCDC3 Load Transient Response
TPS65023-Q1 vdcdc2_vo2_lvs927.gifFigure 17. VDCDC2 Output Voltage Ripple
TPS65023-Q1 startup_vdc_lvs927.gifFigure 19. Startup VDCDC1, VDCDC2, and VDCDC3
TPS65023-Q1 ldo1_lt_lvs927.gifFigure 21. LDO1 Line Transient Response
TPS65023-Q1 vrtc_lt_lvs927.gifFigure 23. VRTC Line Transient Response
TPS65023-Q1 ldo2_ld_lvs927.gifFigure 25. LDO2 Load Transient Response