SLVSAF7C September   2010  – April 2019 TPS61251

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Limit Operation
      2. 9.3.2 Soft Start
      3. 9.3.3 Enable
      4. 9.3.4 Undervoltage Lockout (UVLO)
      5. 9.3.5 Power Good
      6. 9.3.6 Input Overvoltage Protection
      7. 9.3.7 Load Disconnect and Reverse Current Protection
      8. 9.3.8 Thermal Regulation
      9. 9.3.9 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Save Mode
      2. 9.4.2 Snooze Mode
      3. 9.4.3 100% Duty-Cycle Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Output Voltage Setting
        3. 10.2.2.3 Average Input Current Limit
        4. 10.2.2.4 Maximum Output Current
        5. 10.2.2.5 Inductor Selection
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
        8. 10.2.2.8 Checking Loop Stability
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Consideration
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Development Support
      1. 13.2.1 Custom Design With WEBENCH® Tools
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resource
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

10.2.2.8 Checking Loop Stability

The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:

  • Switching node, SW
  • Inductor current, IL
  • Output ripple voltage, VOUT(AC)

These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.

As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the load transient takes place and the turn on of the PMOS switch, the output capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when the device operates in PWM mode.

During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45°C of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range.