SLVSAF7C September   2010  – April 2019 TPS61251

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Limit Operation
      2. 9.3.2 Soft Start
      3. 9.3.3 Enable
      4. 9.3.4 Undervoltage Lockout (UVLO)
      5. 9.3.5 Power Good
      6. 9.3.6 Input Overvoltage Protection
      7. 9.3.7 Load Disconnect and Reverse Current Protection
      8. 9.3.8 Thermal Regulation
      9. 9.3.9 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Save Mode
      2. 9.4.2 Snooze Mode
      3. 9.4.3 100% Duty-Cycle Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Output Voltage Setting
        3. 10.2.2.3 Average Input Current Limit
        4. 10.2.2.4 Maximum Output Current
        5. 10.2.2.5 Inductor Selection
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
        8. 10.2.2.8 Checking Loop Stability
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Consideration
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Development Support
      1. 13.2.1 Custom Design With WEBENCH® Tools
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resource
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9.1 Overview

The TPS61251 boost converter operates as a quasi-constant frequency adaptive on-time controller. In a typical application the frequency is 3.5 MHz and is defined by the input to output voltage ratio and does not vary from moderate to heavy load currents. At light load the converter automatically enters power-save mode and operates in pulse frequency modulation (PFM) mode. During PWM operation the converter uses a unique fast response quasi-constant on-time valley current mode controller scheme which offers excellent line and load regulation and the use of small ceramic input capacitors.

Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low-side N-MOS switch is turned on and the inductor current ramps up to a peak current that is defined by the on-time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned on and the inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.

The TPS61251 device directly and accurately controls the average input current through intelligent adjustment of the valley current limit, allowing an accuracy of ±10% at 500-mA average input current. Together with an external bulk capacitor the TPS61251 device allows an application to be interfaced directly to its load, without overloading the input source due to appropriate set average input current limit.

High values of output capacitance are mainly achieved by putting capacitors in parallel. This reduces the overall series resistance (ESR) to very low values. This results in almost no voltage ripple at the output and therefore the regulation circuit has no voltage drop to react on. Nevertheless to ensure accurate output voltage regulation even with very low ESR the regulation loop can switch to a pure comparator regulation scheme. During this operation the output voltage is regulated between two thresholds. The upper threshold is defined by the programmed output voltage and the lower value is about 10 mV lower. If the upper threshold is reached the off-time is increased to reduce the current in the inductor. Therefore the output voltage will slightly drop until the lower threshold is tripped. Now the off-time is reduced to increase the current in the inductor to charge up the output voltage to the steady-state value. The current swing during this operation mode is strongly depending on the current drawn by the load but will not exceed the programmed current limit. The output voltage during comparator operation stays within the specified accuracy with minimum voltage ripple.

This architecture with adaptive slope compensation provides excellent transient load response and requiring minimal output filtering. Internal softstart and loop compensation simplifies the design process while minimizing the number of external components.