SLVSB16E November   2011  – December 2015 TPS43340-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Inputs
      2. 7.3.2 Linear Regulator (LREG1)
      3. 7.3.3 Gate-Driver Supply (VREG, EXTSUP)
      4. 7.3.4 External P-Channel Drive (GPULL) and Reverse Battery Protection
      5. 7.3.5 Undervoltage Lockout and Overvoltage Protection
      6. 7.3.6 Synchronous Buck Converter Buck3
        1. 7.3.6.1 Soft Start and Foldback Functions
        2. 7.3.6.2 Current-Mode Control and Current-Limit Protection
        3. 7.3.6.3 Operation in Dropout and Undervoltage Protection
        4. 7.3.6.4 Slew Rate Control (SLEW)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.4.1.1 Setting the Operating Frequency
        2. 7.4.1.2 Feedback Inputs
        3. 7.4.1.3 Soft-Start Inputs
        4. 7.4.1.4 Current-Mode Operation
        5. 7.4.1.5 Current Sensing and Current Limit With Foldback
        6. 7.4.1.6 Slope Compensation
        7. 7.4.1.7 Reset Outputs and Filter Delays
        8. 7.4.1.8 Light-Load PFM Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High- and Low-Side Power NMOS Selection for the Buck Converters
        2. 8.2.2.2 Buck1 Component Selection
        3. 8.2.2.3 Buck2 Component Selection
        4. 8.2.2.4 Buck3 Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
      1. 10.3.1 Power Dissipation of Buck1 and Buck2 (VOUT1 and VOUT2)
      2. 10.3.2 Power Dissipation of Buck Converter Buck3 (VOUT3)
        1. 10.3.2.1 High-Side Switch
        2. 10.3.2.2 Low-Side Switch
        3. 10.3.2.3 Linear Regulator (LREG1)
        4. 10.3.2.4 IC Power Consumption
    4. 10.4 Thermal Considerations
      1. 10.4.1 Phase Configuration
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power Supply Recommendations

The TPS43340-Q1 is designed to operate from an input voltage up to 40 V for the buck controllers (Buck1, Buck2). The buck converter (Buck3) accepts input voltages up to 10 V; so in many applications, the output of Buck1 or Buck2 is used to supply it. The linear regulator accepts up to 40 V; however, for power dissipation reasons, TI advises using lower supply voltages. Ensure that the supply for all inputs is well regulated. Furthermore, if the supply voltage in the application is likely to reach negative voltage (for example, reverse battery), a forward diode must be placed at the input of the supply, where GPULL-pin can be used to bypass the diode with an external FET to reduce the voltage drop and power dissipation. For the VIN pin, place a ceramic capacitor or a set of ceramic capacitors close to the pin and add more capacitance as required. Consider capacitance derating for aging, temperature, and DC bias. The PowerPAD package, which offers an exposed thermal pad to enhance thermal performance, must be soldered to the copper landing on the PCB for optimal performance.

  • Connect a local decoupling capacitor close to the VSUP pin (supply for Buck3) for proper filtering.
  • Connect a local decoupling capacitor close to the VLR1 pin (supply for LDO) for proper filtering.
  • Connect a local decoupling capacitor close to the VREG-pin for proper filtering.