SLVSB69C June   2012  – September 2021 TPS54719

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency PWM Control
      2. 7.3.2 Slope Compensation And Output Current
      3. 7.3.3 Bootstrap Voltage (Boot) And Low Dropout Operation
      4. 7.3.4 Error Amplifier
      5. 7.3.5 Voltage Reference
      6. 7.3.6 Adjusting The Output Voltage
      7. 7.3.7 Enable and Adjusting Undervoltage Lockout
      8. 7.3.8 Slow Start/Tracking Pin
      9. 7.3.9 Sequencing
    4. 7.4 Device Functional Modes
      1. 7.4.1  Constant Switching Frequency And Timing Resistor (RT Pin)
      2. 7.4.2  Overcurrent Protection
      3. 7.4.3  Frequency Shift
      4. 7.4.4  Reverse Overcurrent Protection
      5. 7.4.5  Power Good (PWRGD Pin)
      6. 7.4.6  Overvoltage Transient Protection
      7. 7.4.7  Thermal Shutdown
      8. 7.4.8  Small Signal Model For Loop Response
      9. 7.4.9  Simple Small Signal Model For Peak Current Mode Control
      10. 7.4.10 Small Signal Model For Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Frequency, 1.8-V Output Power Supply Design With Adjusted UVLO
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Selecting The Switching Frequency
        2. 8.2.3.2 Output Inductor Selection
        3. 8.2.3.3 Output Capacitor
        4. 8.2.3.4 Input Capacitor
        5. 8.2.3.5 Slow-Start Capacitor
        6. 8.2.3.6 Bootstrap Capacitor Selection
        7. 8.2.3.7 Undervoltage Lockout Set Point
        8. 8.2.3.8 Output Voltage And Feedback Resistors Selection
        9. 8.2.3.9 Compensation
      4. 8.2.4 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load, such as transitioning from no load to a full load. The regulator response to the load step change is limited by the control loop bandwidth, FCO. The output capacitor must be sized to supply the extra current without excessive output voltage drop until the control loop can respond to the load change. Equation 25 shows the minimum output capacitance necessary for an instantaneous load step change. Practical circuits will have a slew rate limited load step and will typically require less capacitance.

For this example, the transient load response is specified as a 6% change in Vout for a load step from 1.75 A (25%) to 5.25 A (75%), and ΔVout = 0.06 × 1.8 = 108 mV. For a load step slew rate of 30 mA / µsec, 2 × 22 µF is sufficient to meet the voltage drop requirement. The ESR of the output capacitor is ignored as the ESR of ceramic capacitors is small.

Equation 26 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 26 yields 14 µF.

Equation 25. GUID-A30B7815-4EAF-427E-A798-FC4717E1A958-low.gif
Equation 26. GUID-D73B8651-892E-4B28-B387-539313D58F05-low.gif

where:

  • ΔIout is the change in output current
  • Fsw is the regulators switching frequency
  • ΔVout is the allowable change in the output voltage
  • Vripple is the maximum allowable output voltage ripple
  • Iripple is the inductor ripple current

Equation 27 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 27 indicates the ESR should be less than 28.6 mΩ. In this case, the ESR of the ceramic capacitor is much less than 17.9 mΩ.

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, two 22-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR are used.

Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 28 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 28 yields 485 mA.

Equation 27. GUID-BFCE4F32-333F-4085-98B3-E46592BA685A-low.gif
Equation 28. GUID-63A6F718-73B4-4175-9D02-D95B03454259-low.gif