SLVSB97 Data sheet

SLVSB97E July 2012 – January 2018 TPS23751 , TPS23752

PRODUCTION DATA.

6.8 Electrical Characteristics - PoE Interface Section

Unless otherwise noted, 40 V ≤ V_DD ≤ 57 V; V_CTL = V_MODE = V_SLPb = V_B; V_SRT = 0.5 V; V_APD = V_CS = V_ARTN = V_RTN; CLS, GATE, LED, SRD, T2P open; R_WAKE = 392 kΩ; R_DEN = 24.9 kΩ; R_T = 34 kΩ; C_VB = C_VC = 0.1 µF;
–40 ≤ T_J ≤ 125°C. Typical values are at 25°C. All voltages referred to V_SS.
Unless otherwise noted, V_VC = V_APD = V_CS = V_ARTN = V_RTN.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DEN (DETECTION AND ENABLE)
	Bias current	DEN open, I_VDD + I_DEN + I_RTN, V_VDD = 10.1 V, not in mark	3	5	12	µA
	DEN leakage current	V_DEN = V_VDD = 57 V		0.1	5	µA
	Detection current	I_VDD + I_DEN + I_RTN, V_VDD = 1.4 V	53.8	56.5	58.3	µA
	Detection current	I_VDD + I_DEN + I_RTN, V_VDD = 10.1 V	395	410	417	µA
V_{PD_DIS}	Disable threshold	DEN falling	3	3.6	5	V
V_{PD_DIS}	Hysteresis		50	113	200	mV
CLS (CLASSIFICATION)
I_CLS	Classification current	13 V ≤ V_VDD ≤ 21 V, Measure I_VDD + I_DEN + I_RTN				mA
		R_CLS = 1270 Ω	1.80	2.17	2.60
		R_CLS = 243 Ω	9.90	10.60	11.20
		R_CLS = 137 Ω	17.60	18.60	19.40
		R_CLS = 90.9 Ω	26.50	27.90	29.30
		R_CLS = 63.4 Ω	38.00	39.90	42.00
V_{CL_ON} V_{CL_H}	Class lower threshold	V_VDD rising, V_CLS ↑	11.9	12.5	13	V
V_{CL_ON} V_{CL_H}	Class lower threshold	Hysteresis	1.4	1.6	1.7	V
V_{CU_OFF} V_{CU_H}	Class upper threshold	V_VDD rising, V_CLS ↓	21	22	23	V
V_{CU_OFF} V_{CU_H}	Class upper threshold	Hysteresis	0.50	0.75	0.90	V
V_MSR	Mark reset threshold	V_VDD falling	3	3.9	5	V
	Mark state resistance	2-point measurement at 5 V and 10.1 V	6	9.1	12	kΩ
	Leakage current	V_VDD = 57 V, V_CLS = 0 V, measure I_CLS			1	µA
RTN (PASS DEVICE)
r_DS(on)	On resistance	V_VC= V_APD = V_ARTN = V_CS = V_VDD	0.20	0.45	0.75	Ω
	Current limit	V_VC = V_APD = V_ARTN = V_CS = V_VDD, V_RTN =1.5 V, Measure I_RTN	0.85	1.00	1.20	A
	Inrush current	V_VC = V_APD = V_ARTN = V_CS = V_DD, V_RTN = 2 V, V_DD = 20 V → 48 V	100	140	180	mA
	Inrush termination	Percentage of inrush current	80%	90%	99%
	Foldback threshold	V_RTN ↑	11.0	12.3	13.6	V
	Foldback deglitch time	V_RTN rising to when current limit changes to inrush current limit	500	800	1500	µs
	Input bias current	V_VDD = V_RTN = 30 V, Measure I_RTN			30	µA
	RTN leakage current	V_RTN = V_VDD = 100 V, V_DEN = V_VSS			50	µA
T2P (TYPE 2 PSE INDICATION)
V_T2P	Output low voltage	I_T2P = 2 mA, after 2-event classification and softstart is complete, V_VC = 12 V, V_CTL = 3 V, V_ARTN = V_VSS		0.26	0.60	V
t_T2P	T2P startup delay	V_CTL = 3 V, V_APD = 2 V, Measure from switching start to V_T2P ↓	2	4.3	7	ms
	Leakage current	V_T2P = 18 V, V_ARTN = V_VSS			10	µA
PoE – PD UVLO
V_{UVLO_R}	UVLO rising threshold		36.3	38.1	40	V
V_{UVLO_R}	UVLO falling threshold		30.5	32.0	33.6	V
SUPPLY CURRENT
	Operating current	Measure I_VDD, V_VDD = 48 V, 40 V ≤ V_VDD ≤ 57 V		210	500	µA
	Off-state current	ARTN and V_VC open, V_VDD = 30 V, Measure I_VDD			300	µA
THERMAL SHUTDOWN
	Shutdown	T_Jrising	135	145	155	°C
	Hysteresis ⁽¹⁾			20		°C

(1) Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.

TPS23751 TPS23752 Curr_Mode_Comp_Ramp_SLVSB97.gif

Figure 1. Current Mode Compensation Ramp

TPS23751 TPS23752 Time_Delay_SLVSB97.gif

Figure 2. Time Delay from V_CS to V_GATE

TPS23751 TPS23752 Rise_Fall_Time_SLVSB97.gif

Figure 3. Rise Time and Fall Time of V_GATE