SLVSCK1A April   2014  – April 2014 TPS65980

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 2.5-V to 15.75-V Input
      2. 8.3.2 3.3-V Outputs
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Cable Power Out Current Limit
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with 2.5 V ≤ VTBT_IN ≤ 3.4 V
      2. 8.4.2 Operation with 10 V ≤ VTBT_IN ≤ 15.75 V
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Single-Port Bus-Powered Thunderbolt™ Device
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
      2. 9.2.2 Dual-Port Bus-Powered Thunderbolt™ Device
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9 Application and Implementation

9.1 Application Information

The TPS65980 DC/DC switching regulator that receives power from a Thunderbolt™ or Thunderbolt™ 2 power bus ranging from 2.5 V to 15.75 V and generates three separate 3.3-V supply outputs.

9.2 Typical Application

9.2.1 Single-Port Bus-Powered Thunderbolt™ Device

typ_app_slvsck1.gifFigure 13. Typical Application (Single-Port Bus-Powered Thunderbolt™ Device)

9.2.1.1 Design Requirements

Table 1. Recommended Component Values

COMPONENT DESCRIPTION MIN TYP MAX UNIT
CIN TBT_IN Input Capacitance 17.6 22 52 µF
CBOOT Converter Bootstrap Capacitance 8 10 12 nF
CCP Charge Pump Capacitance (ceramic with ESR ≤ 10 mΩ) 0.8 1 1.2 µF
CSS Soft Start Capacitance 8 10 12 nF
CTBT TBT_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ) 16 20 24 µF
CCBL CBL_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ) 0.8 1 1.2 µF
CDEV DEV_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ) 0.8 1 1.2 µF
CC Compensation Capacitance 8 10 12 nF
RC Compensation Resistance 8 10 12 kΩ
L Inductor SRR1280 (ESR ≤ 20 mΩ) 8 10 12 µH

9.2.1.2 Detailed Design Procedure

The TPS65980 should use the recommended component values in Table 1. The device is designed to fit the needs of a Thunderbolt™ bus powered peripheral and the recommended component values are chosen to satisfy those conditions. The input capacitance CIN can be as high as 52 µF, but this maximum capacitance must include all capacitances seen at the input to the Thunderbolt™ port.

9.2.1.3 Application Performance Plots

app_plot1_slvsck1.gif
CTBT_OUT = 10 µF VTBT_IN = 12 V
Figure 14. TBT_OUT Load Transient Response
(0.5A to 3.5A Step)
app_plot3_slvsck1.gif
Figure 16. 0V to 3.3V Power Up With 50mA Load
app_plot5_slvsck1.gif
Figure 18. 3.3V to 15.75V Vin Step With 50mA Load
app_plot7_slvsck1.gif
CBL_ILIMIT = 0
Figure 20. Short Circuit Current Limit Response
app_plot2_slvsck1.gif
CTBT_OUT = 10 µF VTBT_IN = 12 V
Figure 15. TBT_OUT Load Transient Response
(3.5A to 0.5A Step)
app_plot4_slvsck1.gif
Figure 17. 3.3V to 0V Power Down With 50mA Load
app_plot6_slvsck1.gif
Figure 19. 15.75 to 3.3V Vin Step With 50mA Load
app_plot8_slvsck1.gif
CBL_ILIMIT = 1
Figure 21. Short Circuit Current Limit Response

9.2.2 Dual-Port Bus-Powered Thunderbolt™ Device

typ_app_dp_slvsck1.gifFigure 22. Typical Application (Dual-Port Bus-Powered Thunderbolt™ Device)

9.2.2.1 Design Requirements

In a dual-port application, the TBT_IN input voltage will be selected from either port. A simple diode-or function will produce TBT_IN from the higher of the two inputs. The diode-or selection will allow the high-voltage supply to be at TBT_IN.

In a dual port system, the TPS65980 must provide cable power to both ports. In this case, a second current limiting device (TPS22920) connected between TBT_OUT and the port is recommended. The CBL_OUT pin can also supply current to both ports. In this case, tying CBL_ILIMIT to TBT_OUT will double the amount of current that can be supplied before current limiting. When using this method, the voltage drop to the CBL_OUT pin will increase and care must be taken that other systems resistance do not cause the cable voltage to drop below the allowed pin voltage specified in the Thunderbolt™ specification. To avoid issues with voltage drop in the system, it is recommended that the second port be powered from TBT_OUT as shown in Figure 22. This relieves the voltage drop due to extra current through the CBL_OUT load switch.

Table 2. Recommended Component Values

COMPONENT DESCRIPTION MIN TYP MAX UNIT
CIN TBT_IN Input Capacitance 17.6 22 52 µF
CBOOT Converter Bootstrap Capacitance 8 10 12 nF
CCP Charge Pump Capacitance (ceramic with ESR ≤ 10 mΩ) 0.8 1 1.2 µF
CSS Soft Start Capacitance 8 10 12 nF
CTBT TBT_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ) 16 20 24 µF
CCBL CBL_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ) 0.8 1 1.2 µF
CDEV DEV_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ) 0.8 1 1.2 µF
CC Compensation Capacitance 8 10 12 nF
RC Compensation Resistance 8 10 12 kΩ
L Inductor SRR1280 (ESR ≤ 20 mΩ) 8 10 12 µH

9.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure in the Single-Port Bus-Powered Thunderbolt™ Device section.

9.2.2.3 Application Performance Plots

Refer to Application Performance Plots in the Single-Port Bus-Powered Thunderbolt™ Device section.