SLVSCK1A April   2014  – April 2014 TPS65980

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 2.5-V to 15.75-V Input
      2. 8.3.2 3.3-V Outputs
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Cable Power Out Current Limit
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with 2.5 V ≤ VTBT_IN ≤ 3.4 V
      2. 8.4.2 Operation with 10 V ≤ VTBT_IN ≤ 15.75 V
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Single-Port Bus-Powered Thunderbolt™ Device
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
      2. 9.2.2 Dual-Port Bus-Powered Thunderbolt™ Device
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

11 Layout

11.1 Layout Guidelines

Proper placement and routing will maximize the performance of the TPS65980. Follow Figure 23 for optimized layout and routing (hashed planes indicate bottom layer).

11.2 Layout Example

layout_enh_slvsck1.gifFigure 23. Top View Board Layout

For TBT_IN, the input capacitors must be placed close to the device with an inductance less than 1nH from input capacitors to the TBT_IN pins. Layout tools and calculators are available to approximate the inductance. The input capacitors must have their GND side area via stitched to the GND plane. The GND side of the input cap should also share the same polygon as the PGND/PowerPad on the top layer. PowerPad should be connected to the GND plane through multiple vias.

Inductor placement should be above the TPS65980, slightly to the left of the device. The SW pins to the inductor must be connected though a plane as shown in Figure 23. The TBT_OUT pins also have to be connected to the other side of the inductor with a plane. This plane should be wide to overlap the output capacitors. The GND side of the output capacitors should be stitched to the GND plane.

The CBL_OUT output capacitor should be placed close to the device on the top layer with an inductance less than 1 nH from the capacitor to the CBL_OUT pin. The DEV_OUT capacitor is best placed on the bottom side of the board with two planes (top and bottom) connect through a set of vias. The number of vias placed should be able to carry at least 3 A (DEV_OUT = 2.5 A max) for margin and inductance path less than 1nH from DEV_OUT pins to capacitor. When routing DEV_OUT to an internal power plane, follow Figure 24 for via paths.

dev_out_slvsck1.gifFigure 24. DEV_OUT Recommended Routing

The charge pump capacitor must be placed on the top layer close to the CPP and CPN pins. The inductance paths from capacitor to the pins must be less than 1 nH. SS and Compensation components should be placed on the top layer close to the device.