SLVSDR2B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

7.6 Register Maps

Memory Map lists all the ADC12DJ3200QML-SP registers.

Table 7-44
ADDRESS RESET ACRONYM TYPE REGISTER NAME
STANDARD SPI-3.0 (0x000 to 0x00F)
0x000 0x30 CONFIG_A R/W Configuration A Register
0x001 Undefined RESERVED R RESERVED
0x002 0x00 DEVICE_CONFIG R/W Device Configuration Register
0x003 0x03 CHIP_TYPE R Chip Type Register
0x004-0x005 0x0020 CHIP_ID R Chip ID Registers
0x006 0x0A CHIP_VERSION R Chip Version Register
0x007-0x00B Undefined RESERVED R RESERVED
0x00C-0x00D 0x0451 VENDOR_ID R Vendor Identification Register
0x00E-0x00F Undefined RESERVED R RESERVED
USER SPI CONFIGURATION (0x010 to 0x01F)
0x010 0x00 USR0 R/W User SPI Configuration Register
0x011-0x01F Undefined RESERVED R RESERVED
MISCELLANEOUS ANALOG REGISTERS (0x020 to 0x047)
0x020-0x028 Undefined RESERVED R RESERVED
0x029 0x00 CLK_CTRL0 R/W Clock Control Register 0
0x02A 0x20 CLK_CTRL1 R/W Clock Control Register 1
0x02B Undefined RESERVED R RESERVED
0x02C-0x02E Undefined SYSREF_POS R SYSREF Capture Position Register
0x02F Undefined RESERVED R RESERVED
0x030-0x031 0xA000 FS_RANGE_A R/W INA Full-Scale Range Adjust Register
0x032-0x033 0xA000 FS_RANGE_B R/W INB Full-Scale Range Adjust Register
0x034-0x037 Undefined RESERVED R RESERVED
0x038 0x00 BG_BYPASS R/W Internal Reference Bypass Register
0x039-0x03A Undefined RESERVED R RESERVED
0x03B 0x00 TMSTP_CTRL R/W TMSTP± Control Register
0x03C-0x047 Undefined RESERVED R RESERVED
SERIALIZER REGISTERS (0x048 to 0x05F)
0x048 0x00 SER_PE R/W Serializer Pre-Emphasis Control Register
0x049-0x05F Undefined RESERVED R RESERVED
CALIBRATION REGISTERS (0x060 to 0x0FF)
0x060 0x01 INPUT_MUX R/W Input Mux Control Register
0x061 0x01 CAL_EN R/W Calibration Enable Register
0x062 0x01 CAL_CFG0 R/W Calibration Configuration 0 Register
0x063-0x069 Undefined RESERVED R RESERVED
0x06A Undefined CAL_STATUS R Calibration Status Register
0x06B 0x00 CAL_PIN_CFG R/W Calibration Pin Configuration Register
0x06C 0x01 CAL_SOFT_TRIG R/W Calibration Software Trigger Register
0x06D Undefined RESERVED R RESERVED
0x06E 0x88 CAL_LP R/W Low-Power Background Calibration Register
0x06F Undefined RESERVED R RESERVED
0x070 0x00 CAL_DATA_EN R/W Calibration Data Enable Register
0x071 Undefined CAL_DATA R/W Calibration Data Register
0x072-0x079 Undefined RESERVED R RESERVED
0x07A Undefined GAIN_TRIM_A R/W Channel A Gain Trim Register
0x07B Undefined GAIN_TRIM_B R/W Channel B Gain Trim Register
0x07C Undefined BG_TRIM R/W Band-Gap Reference Trim Register
0x07D Undefined RESERVED R RESERVED
0x07E Undefined RTRIM_A R/W VINA Input Resistor Trim Register
0x07F Undefined RTRIM_B R/W VINB Input Resistor Trim Register
0x080 Undefined TADJ_A_FG90 R/W Timing Adjustment for A-ADC, Single-Channel Mode, Foreground Calibration Register
0x081 Undefined TADJ_B_FG0 R/W Timing Adjustment for B-ADC, Single-Channel Mode, Foreground Calibration Register
0x082 Undefined TADJ_A_BG90 R/W Timing Adjustment for A-ADC, Single-Channel Mode, Background Calibration Register
0x083 Undefined TADJ_C_BG0 R/W Timing Adjustment for C-ADC, Single-Channel Mode, Background Calibration Register
0x084 Undefined TADJ_C_BG90 R/W Timing Adjustment for C-ADC, Single-Channel Mode, Background Calibration Register
0x085 Undefined TADJ_B_BG0 R/W Timing Adjustment for B-ADC, Single-Channel Mode, Background Calibration Register
0x086 Undefined TADJ_A R/W Timing Adjustment for A-ADC, Dual-Channel Mode Register
0x087 Undefined TADJ_CA R/W Timing Adjustment for C-ADC Acting for A-ADC, Dual-Channel Mode Register
0x088 Undefined TADJ_CB R/W Timing Adjustment for C-ADC Acting for B-ADC, Dual-Channel Mode Register
0x089 Undefined TADJ_B R/W Timing Adjustment for B-ADC, Dual-Channel Mode Register
0x08A-0x08B Undefined OADJ_A_INA R/W Offset Adjustment for A-ADC and INA Register
0x08C-0x08D Undefined OADJ_A_INB R/W Offset Adjustment for A-ADC and INB Register
0x08E-0x08F Undefined OADJ_C_INA R/W Offset Adjustment for C-ADC and INA Register
0x090-0x091 Undefined OADJ_C_INB R/W Offset Adjustment for C-ADC and INB Register
0x092-0x093 Undefined OADJ_B_INA R/W Offset Adjustment for B-ADC and INA Register
0x094-0x095 Undefined OADJ_B_INB R/W Offset Adjustment for B-ADC and INB Register
0x096 Undefined RESERVED R RESERVED
0x097 0x00 OSFILT0 R/W Offset Filtering Control 0
0x098 0x33 OSFILT1 R/W Offset Filtering Control 1
0x099-0x0FF Undefined RESERVED R RESERVED
ADC BANK REGISTERS (0x100 to 0x15F)
0x100-0x101 Undefined RESERVED R RESERVED
0x102 Undefined B0_TIME_0 R/W Timing Adjustment for Bank 0 (0° Clock) Register
0x103 Undefined B0_TIME_90 R/W Timing Adjustment for Bank 0 (–90° Clock) Register
0x104-0x111 Undefined RESERVED R RESERVED
0x112 Undefined B1_TIME_0 R/W Timing Adjustment for Bank 1 (0° Clock) Register
0x113 Undefined B1_TIME_90 R/W Timing Adjustment for Bank 1 (–90° Clock) Register
0x114-0x121 Undefined RESERVED R RESERVED
0x122 Undefined B2_TIME_0 R/W Timing Adjustment for Bank 2 (0° Clock) Register
0x123 Undefined B2_TIME_90 R/W Timing Adjustment for Bank 2 (–90° Clock) Register
0x124-0x131 Undefined RESERVED R RESERVED
0x132 Undefined B3_TIME_0 R/W Timing Adjustment for Bank 3 (0° Clock) Register
0x133 Undefined B3_TIME_90 R/W Timing Adjustment for Bank 3 (–90° Clock) Register
0x134-0x141 Undefined RESERVED R RESERVED
0x142 Undefined B4_TIME_0 R/W Timing Adjustment for Bank 4 (0° Clock) Register
0x143 Undefined B4_TIME_90 R/W Timing Adjustment for Bank 4 (–90° Clock) Register
0x144-0x151 Undefined RESERVED R RESERVED
0x152 Undefined B5_TIME_0 R/W Timing Adjustment for Bank 5 (0° Clock) Register
0x153 Undefined B5_TIME_90 R/W Timing Adjustment for Bank 5 (–90° Clock) Register
0x154-0x15F Undefined RESERVED R RESERVED
LSB CONTROL REGISTERS (0x160 to 0x1FF)
0x160 0x00 ENC_LSB R/W LSB Control Bit Output Register
0x161-0x1FF Undefined RESERVED R RESERVED
JESD204B REGISTERS (0x200 to 0x20F)
0x200 0x01 JESD_EN R/W JESD204B Enable Register
0x201 0x02 JMODE R/W JESD204B Mode (JMODE) Register
0x202 0x1F KM1 R/W JESD204B K Parameter Register
0x203 0x01 JSYNC_N R/W JESD204B Manual SYNC Request Register
0x204 0x02 JCTRL R/W JESD204B Control Register
0x205 0x00 JTEST R/W JESD204B Test Pattern Control Register
0x206 0x00 DID R/W JESD204B DID Parameter Register
0x207 0x00 FCHAR R/W JESD204B Frame Character Register
0x208 Undefined JESD_STATUS R/W JESD204B, System Status Register
0x209 0x00 PD_CH R/W JESD204B Channel Power-Down
0x20A 0x00 JEXTRA_A R/W JESD204B Extra Lane Enable (Link A)
0x20B 0x00 JEXTRA_B R/W JESD204B Extra Lane Enable (Link B)
0x20C-0x20F Undefined RESERVED R RESERVED
DIGITAL DOWN CONVERTER REGISTERS (0x210-0x2AF)
0x210 0x00 DDC_CFG R/W DDC Configuration Register
0x211 0xF2 OVR_T0 R/W Overrange Threshold 0 Register
0x212 0xAB OVR_T1 R/W Overrange Threshold 1 Register
0x213 0x07 OVR_CFG R/W Overrange Configuration Register
0x214 0x00 CMODE R/W DDC Configuration Preset Mode Register
0x215 0x00 CSEL R/W DDC Configuration Preset Select Register
0x216 0x02 DIG_BIND R/W Digital Channel Binding Register
0x217-0x218 0x0000 NCO_RDIV R/W Rational NCO Reference Divisor Register
0x219 0x02 NCO_SYNC R/W NCO Synchronization Register
0x21A-0x21F Undefined RESERVED R RESERVED
0x220-0x223 0xC0000000 FREQA0 R/W NCO Frequency (DDC A Preset 0)
0x224-0x225 0x0000 PHASEA0 R/W NCO Phase (DDC A Preset 0)
0x226-0x227 Undefined RESERVED R RESERVED
0x228-0x22B 0xC0000000 FREQA1 R/W NCO Frequency (DDC A Preset 1)
0x22C-0x22D 0x0000 PHASEA1 R/W NCO Phase (DDC A Preset 1)
0x22E-0x22F Undefined RESERVED R RESERVED
0x230-0x233 0xC0000000 FREQA2 R/W NCO Frequency (DDC A Preset 2)
0x234-0x235 0x0000 PHASEA2 R/W NCO Phase (DDC A Preset 2)
0x236-0x237 Undefined RESERVED R RESERVED
0x238-0x23B 0xC0000000 FREQA3 R/W NCO Frequency (DDC A Preset 3)
0x23C-0x23D 0x0000 PHASEA3 R/W NCO Phase (DDC A Preset 3)
0x23E-0x23F Undefined RESERVED R RESERVED
0x240-0x243 0xC0000000 FREQB0 R/W NCO Frequency (DDC B Preset 0)
0x244-0x245 0x0000 PHASEB0 R/W NCO Phase (DDC B Preset 0)
0x246-0x247 Undefined RESERVED R RESERVED
0x248-0x24B 0xC0000000 FREQB1 R/W NCO Frequency (DDC B Preset 1)
0x24C-0x24D 0x0000 PHASEB1 R/W NCO Phase (DDC B Preset 1)
0x24E-0x24F Undefined RESERVED R RESERVED
0x250-0x253 0xC0000000 FREQB2 R/W NCO Frequency (DDC B Preset 2)
0x254-0x255 0x0000 PHASEB2 R/W NCO Phase (DDC B Preset 2)
0x256-0x257 Undefined RESERVED R RESERVED
0x258-0x25B 0xC0000000 FREQB3 R/W NCO Frequency (DDC B Preset 3)
0x25C-0x25D 0x0000 PHASEB3 R/W NCO Phase (DDC B Preset 3)
0x25E-0x296 Undefined RESERVED R RESERVED
0x297 Undefined SPIN_ID R Spin Identification Value
0x298-0x2AF Undefined RESERVED R RESERVED
SYSREF CALIBRATION REGISTERS (0x2B0 to 0x2BF)
0x2B0 0x00 SRC_EN R/W SYSREF Calibration Enable Register
0x2B1 0x05 SRC_CFG R/W SYSREF Calibration Configuration Register
0x2B2-0x2B4 Undefined SRC_STATUS R SYSREF Calibration Status
0x2B5-0x2B7 0x00 TAD R/W DEVCLK Aperture Delay Adjustment Register
0x2B8 0x00 TAD_RAMP R/W DEVCLK Timing Adjust Ramp Control Register
0x2B9-0x2BF Undefined RESERVED R RESERVED
ALARM REGISTERS (0x2C0 to 0x2C2)
0x2C0 Undefined ALARM R Alarm Interrupt Status Register
0x2C1 0x1F ALM_STATUS R/W Alarm Status Register
0x2C2 0x1F ALM_MASK R/W Alarm Mask Register