SLVSDR2B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

7.4.3.1 JESD204B Output Data Formats

Output data are formatted in a specific optimized fashion for each JMODE setting. When the DDC is not used (decimation = 1) the 12-bit offset binary values are mapped into octets. For the DDC mode, the 16-bit values (15-bit complex data plus 1 overrange bit) are mapped into octets. The following tables show the specific mapping formats for a single frame. In all mappings the tail bits (T) are 0 (zero). In Table 7-20 to Table 7-37, the single-channel format samples are defined as Sn, where n is the sample number within the frame. In the dual-channel real output formats (DDC bypass and decimate-by-2), the samples are defined as An and Bn, where An are samples from channel A and Bn are samples from channel B. In the complex output formats (decimate-by-4, decimate-by-8, decimate-by-16), the samples are defined as AIn, AQn, BIn and BQn, where AIn and AQn are the in-phase and quadrature-phase samples of channel A and BIn and BQn are the in-phase and quadrature-phase samples of channel B. All samples are formatted as MSB first, LSB last.

Table 7-20 JMODE 0 (12-bit, Decimate-by-1, Single-Channel, 8 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0S0S8S16S24S32T
DA1S2S10S18S26S34T
DA2S4S12S20S28S36T
DA3S6S14S22S30S38T
DB0S1S9S17S25S33T
DB1S3S11S19S27S35T
DB2S5S13S21S29S37T
DB3S7S15S23S31S39T
Table 7-21 JMODE 1 (12-Bit, Decimate-by-1, Single-Channel, 16 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0S0S16S32S48S64T
DA1S2S18S34S50S66T
DA2S4S20S36S52S68T
DA3S6S22S38S54S70T
DA4S8S24S40S56S72T
DA5S10S26S42S58S74T
DA6S12S28S44S60S76T
DA7S14S30S46S62S78T
DB0S1S17S33S49S65T
DB1S3S19S35S51S67T
DB2S5S21S37S53S69T
DB3S7S23S39S55S71T
DB4S9S25S41S57S73T
DB5S11S27S43S59S75T
DB6S13S29S45S61S77T
DB7S15S31S47S63S79T
Table 7-22 JMODE 2 (12-Bit, Decimate-by-1, Dual-Channel, 8 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0A0A4A8A12A16T
DA1A1A5A9A13A17T
DA2A2A6A10A14A18T
DA3A3A7A11A15A19T
DB0B0B4B8B12B16T
DB1B1B5B9B13B17T
DB2B2B6B10B14B18T
DB3B3B7B11B15B19T
Table 7-23 JMODE 3 (12-Bit, Decimate-by-1, Dual-Channel, 16 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0A0A8A16A24A32T
DA1A1A9A17A25A33T
DA2A2A10A18A26A34T
DA3A3A11A19A27A35T
DA4A4A12A20A28A36T
DA5A5A13A21A29A37T
DA6A6A14A22A30A38T
DA7A7A15A23A31A39T
DB0B0B8B16B24B32T
DB1B1B9B17B25B33T
DB2B2B10B18B26B34T
DB3B3B11B19B27B35T
DB4B4B12B20B28B36T
DB5B5B13B21B29B37T
DB6B6B14B22B30B38T
DB7B7B15B23B31B39T
Table 7-24 JMODE 4 (8-Bit, Decimate-by-1, Single-Channel, 4 Lanes)
OCTET0
NIBBLE01
DA0S0
DA1S2
DB0S1
DB1S3
Table 7-25 JMODE 5 (8-Bit, Decimate-by-1, Single-Channel, 8 Lanes)
OCTET0
NIBBLE01
DA0S0
DA1S2
DA2S4
DA3S6
DB0S1
DB1S3
DB2S5
DB3S7
Table 7-26 JMODE 6 (8-Bit, Decimate-by-1, Dual-Channel, 4 Lanes)
OCTET0
NIBBLE01
DA0A0
DA1A1
DB0B0
DB1B1
Table 7-27 JMODE 7 (8-Bit, Decimate-by-1, Dual-Channel, 8 Lanes)
OCTET0
NIBBLE01
DA0A0
DA1A1
DA2A2
DA3A3
DB0B0
DB1B1
DB2B2
DB3B3
Table 7-28 JMODE 9 (15-Bit, Decimate-by-2, Dual-Channel, 8 Lanes)
OCTET01
NIBBLE0123
DA0A0
DA1A1
DA2A2
DA3A3
DB0B0
DB1B1
DB2B2
DB3B3
Table 7-29 JMODE 10 (15-Bit, Decimate-by-4, Dual-Channel, 4 Lanes)
OCTET01
NIBBLE0123
DA0AI0
DA1AQ0
DB0BI0
DB1BQ0
Table 7-30 JMODE 11 (15-Bit, Decimate-by-4, Dual-Channel, 8 Lanes)
OCTET01
NIBBLE0123
DA0AI0
DA1AI1
DA2AQ0
DA3AQ1
DB0BI0
DB1BI1
DB2BQ0
DB3BQ1
Table 7-31 JMODE 12 (12-Bit, Decimate-by-4, Dual-Channel, 16 Lanes)
OCTET01234567
NIBBLE0123456789101112131415
DA0AI0AI4AI8AI12AI16T
DA1AQ0AQ4AQ8AQ12AQ16T
DA2AI1AI5AI9AI13AI17T
DA3AQ1AQ5AQ9AQ13AQ17T
DA4AI2AI6AI10AI14AI18T
DA5AQ2AQ6AQ10AQ14AQ218T
DA6AI3AI7AI11AI15AI19T
DA7AQ3AQ7AQ11AQ15AQ19T
DB0BI0BI4BI8BI12BI16T
DB1BQ0BQ4BQ8BQ12BQ16T
DB2BI1BI5BI9BI13BI17T
DB3BQ1BQ5BQ9BQ13BQ17T
DB4BI2BI6BI10BI14BI18T
DB5BQ2BQ6BQ10BQ14BQ218T
DB6BI3BI7BI11BI15BI19T
DB7BQ3BQ7BQ11BQ15BQ19T
Table 7-32 JMODE 13 (15-Bit, Decimate-by-8, Dual-Channel, 2 Lanes)
OCTET0123
NIBBLE01234567
DA0AI0AQ0
DB0BI0BQ0
Table 7-33 JMODE 14 (15-Bit, Decimate-by-8, Dual-Channel, 4 Lanes)
OCTET01
NIBBLE0123
DA0AI0
DA1AQ0
DB0BI0
DB1BQ0
Table 7-34 JMODE 15 (15-Bit, Decimate-by-16, Dual-Channel, 1 Lane)
OCTET01234567
NIBBLE0123456789101112131415
DA0AI0AQ0BI0BQ0
Table 7-35 JMODE 16 (15-Bit, Decimate-by-16, Dual-Channel, 2 Lanes)
OCTET0123
NIBBLE01234567
DA0AI0AQ0
DB0BI0BQ0
Table 7-36 JMODE 17 (8-bit, Decimate-by-1, Single-Channel, 16 lanes)
OCTET0
NIBBLE01
DA0S0
DA1S2
DA2S4
DA3S6
DA4S8
DA5S10
DA6S12
DA7S14
DB0S1
DB1S3
DB2S5
DB3S7
DB4S9
DB5S11
DB6S13
DB7S15
Table 7-37 JMODE 18 (8-Bit, Decimate-by-1, Dual-Channel, 16 Lanes)
OCTET0
NIBBLE01
DA0A0
DA1A1
DA2A2
DA3A3
DA4A4
DA5A5
DA6A6
DA7A7
DB0B0
DB1B1
DB2B2
DB3B3
DB4B4
DB5B5
DB6B6
DB7B7